From fc7bfddd64360e7b991a30412227eac665cd8563 Mon Sep 17 00:00:00 2001
From: Rodrigo Arias Mallo <rodrigo.arias@bsc.es>
Date: Fri, 12 Jul 2024 18:47:48 +0200
Subject: [PATCH] Switch to openpiton configuration

---
 JOURNAL.md     | 35 +++++++++++++++++++++++++++++++++++
 lagarto-ox.nix |  4 ++--
 ox-plic.dts    | 24 ++++++++++++------------
 3 files changed, 49 insertions(+), 14 deletions(-)

diff --git a/JOURNAL.md b/JOURNAL.md
index 99576df..4e69a0f 100644
--- a/JOURNAL.md
+++ b/JOURNAL.md
@@ -2513,3 +2513,38 @@ With this regions:
 I will also try 0x80013000 as address as I saw it being used before, but I don't
 think it is the problem. It must be related with how the initialization is now
 different.
+
+    OpenSBI v1.4
+       ____                    _____ ____ _____
+      / __ \                  / ____|  _ \_   _|
+     | |  | |_ __   ___ _ __ | (___ | |_) || |
+     | |  | | '_ \ / _ \ '_ \ \___ \|  _ < | |
+     | |__| | |_) |  __/ | | |____) | |_) || |_
+      \____/| .__/ \___|_| |_|_____/|____/_____|
+            | |
+            |_|
+
+    sbi_trap_error: hart0: illegal instruction handler failed (error -2)
+    sbi_trap_error: hart0: mcause=0x0000000000000002 mtval=0x0000000000000000
+    sbi_trap_error: hart0: mepc=0x00000000800131a4 mstatus=0x8000000a00007800
+    sbi_trap_error: hart0: ra=0x0000000080013bb0 sp=0x0000000080046e70
+    sbi_trap_error: hart0: gp=0x0000000000000000 tp=0x0000000080047000
+    sbi_trap_error: hart0: s0=0x0000000080046eb0 s1=0x0000000000000118
+    sbi_trap_error: hart0: a0=0x0000000080013000 a1=0x0000000080046e74
+    sbi_trap_error: hart0: a2=0x00000000800133c0 a3=0x0000000000000600
+    sbi_trap_error: hart0: a4=0x000000000000062c a5=0x0000000000000284
+    sbi_trap_error: hart0: a6=0x0000000000000000 a7=0x000000000000002c
+    sbi_trap_error: hart0: s2=0x0000000080013000 s3=0x0000000000000000
+    sbi_trap_error: hart0: s4=0x0000000080047000 s5=0x0000000000000000
+    sbi_trap_error: hart0: s6=0x0000000000000000 s7=0x0000000000000001
+    sbi_trap_error: hart0: s8=0x0000000000002000 s9=0x00000000800436f0
+    sbi_trap_error: hart0: s10=0x0000000000000000 s11=0x0000000000000000
+    sbi_trap_error: hart0: t0=0x0000000080009796 t1=0x0000000000000268
+    sbi_trap_error: hart0: t2=0x0000000000001000 t3=0x00000000000000d7
+    sbi_trap_error: hart0: t4=0x000000007fffffff t5=0x0000000000000001
+    sbi_trap_error: hart0: t6=0x0000000000000004
+
+With 0x80013000 we seem to enter OpenSBI code region.
+
+Let's try with openpiton again, without the FDT address. We should disable the
+secondary console from the DT too.
diff --git a/lagarto-ox.nix b/lagarto-ox.nix
index faf6624..2dcfe9d 100644
--- a/lagarto-ox.nix
+++ b/lagarto-ox.nix
@@ -312,7 +312,7 @@
       };
       #NIX_DEBUG=5;
       makeFlags = [
-        "PLATFORM=generic"
+        "PLATFORM=fpga/openpiton"
         #"CONFIG_SBI_ECALL_RFENCE=n"
         #"PLATFORM_RISCV_ISA=rv64imafd" # No compressed instructions
         #"PLATFORM_RISCV_ISA=rv64g" # No compressed instructions
@@ -322,7 +322,7 @@
 
         # Ensure it doesn't overlap from the 0x80200000 where the kernel will be
         # placed.
-        "FW_PAYLOAD_FDT_ADDR=0x80013000"
+        #"FW_PAYLOAD_FDT_ADDR=0x80013000"
       ];
       patches = [
         #./opensbi-timer-debug.patch
diff --git a/ox-plic.dts b/ox-plic.dts
index 0f41ba0..6e21697 100644
--- a/ox-plic.dts
+++ b/ox-plic.dts
@@ -7,7 +7,7 @@
 
 	aliases {
 		serial0 = &uart_console; // ttyS0
-		serial1 = &uart_testing; // ttyS1
+//		serial1 = &uart_testing; // ttyS1
 	};
 
 //	chosen {
@@ -128,17 +128,17 @@
 			current-speed = <115200>;
 			status = "okay";
 		};
-		/* The serial for interrupt tests */
-		uart_testing: serial@40003000 {
-			compatible = "ns16550";
-			reg = <0x0 0x40003000 0x0 0x1000>;
-//			interrupts = <1>; /* Output interrupt 1 */
-//			interrupt-parent = <&PLIC>;
-			reg-shift = <2>;
-			clock-frequency = <50000000>;
-			current-speed = <115200>;
-			status = "okay";
-		};
+//		/* The serial for interrupt tests */
+//		uart_testing: serial@40003000 {
+//			compatible = "ns16550";
+//			reg = <0x0 0x40003000 0x0 0x1000>;
+////			interrupts = <1>; /* Output interrupt 1 */
+////			interrupt-parent = <&PLIC>;
+//			reg-shift = <2>;
+//			clock-frequency = <50000000>;
+//			current-speed = <115200>;
+//			status = "okay";
+//		};
 
 //		ethernet0 {
 //			xlnx,rxmem = <0x000005f2>;