From e67965cc0ae269e94d26455b86ce1de1f8521f54 Mon Sep 17 00:00:00 2001
From: Rodrigo Arias Mallo <rodarima@gmail.com>
Date: Fri, 2 Aug 2024 10:33:31 +0200
Subject: [PATCH] Always enable external machine mode interrupts

---
 JOURNAL.md                  | 49 ++++++++++++++++++++++++++++++++++---
 opensbi-dont-delegate.patch | 24 ++++++++++++++++++
 2 files changed, 70 insertions(+), 3 deletions(-)

diff --git a/JOURNAL.md b/JOURNAL.md
index 154f370..6c00508 100644
--- a/JOURNAL.md
+++ b/JOURNAL.md
@@ -2595,7 +2595,7 @@ be able to generate an interrupt.
 
 Here is the comment where I gather the pieces:
 
----8<---
+---8<---{{{
 
 From https://gitlab.bsc.es/hwdesign/rtl/core-tile/sa-fpga/ I can see that the
 auxiliary timer [is in fact another
@@ -2695,7 +2695,7 @@ The memory map would need a bit of adjustment in the device tree, but to play wi
 
 I think I have all the pieces now.
 
----8<---
+---8<---}}}
 
 I will try with the last bitstream that I already had compiled, as I will have
 to rebuild the required packages in nix.
@@ -3037,7 +3037,7 @@ From `include/sbi/riscv_encoding.h`:
     #define IRQ_VS_SOFT			2
     #define IRQ_M_SOFT			3
     #define IRQ_S_TIMER			5
-    #define IRQ_VS_TIMER			6
+    #define IRQ_VS_TIMER		6
     #define IRQ_M_TIMER			7
     #define IRQ_S_EXT			9
     #define IRQ_VS_EXT			10
@@ -3254,3 +3254,46 @@ So, I checked again, and I cannot enable the interrupt on context 11:
     => mw 0x40802580 0x10
     => md 0x40802580 1
     40802580: 00000000                             ....
+
+
+Note, the first value is 0 and must be claimed:
+
+    => md 0x40801000 1
+    40801000: 00000010                             ....
+    => md 0x40802000 1
+    40802000: 00000010
+    => md 0x40a00004 1
+    40a00004: 00000000                             ....
+    => mw 0x40a00004 1
+    => mw 0x40a00004 4
+    => md 0x40a00004 1
+    40a00004: 00000004                             ....
+    => mw 0x40a00004 4
+    => md 0x40a00004 1
+    40a00004: 00000004                             ....
+    => mw 0x40a00004 4
+    => md 0x40a00004 1
+    40a00004: 00000004                             ....
+
+## 2024-08-02
+
+I see that the MIE sets the machine mode external interrupt enable in this way:
+
+    int sbi_irqchip_init(struct sbi_scratch *scratch, bool cold_boot)
+    {
+        int rc;
+        const struct sbi_platform *plat = sbi_platform_ptr(scratch);
+
+        rc = sbi_platform_irqchip_init(plat, cold_boot);
+        if (rc)
+            return rc;
+
+        if (ext_irqfn != default_irqfn)
+            csr_set(CSR_MIE, MIP_MEIP);
+
+        return 0;
+    }
+
+Only if the external interrupt function is not the default one. But for the
+PLIC, it looks like the default one is being used. So let's enable the machine
+mode interrupts unconditionally.
diff --git a/opensbi-dont-delegate.patch b/opensbi-dont-delegate.patch
index 5d7388a..343ca93 100644
--- a/opensbi-dont-delegate.patch
+++ b/opensbi-dont-delegate.patch
@@ -11,3 +11,27 @@ index c366701..c5b5249 100644
  	interrupts |= sbi_pmu_irq_bit();
  
  	exceptions = (1U << CAUSE_MISALIGNED_FETCH) | (1U << CAUSE_BREAKPOINT) |
+diff --git a/lib/sbi/sbi_irqchip.c b/lib/sbi/sbi_irqchip.c
+index 0ae604a..dd4592a 100644
+--- a/lib/sbi/sbi_irqchip.c
++++ b/lib/sbi/sbi_irqchip.c
+@@ -37,8 +37,7 @@ int sbi_irqchip_init(struct sbi_scratch *scratch, bool cold_boot)
+ 	if (rc)
+ 		return rc;
+ 
+-	if (ext_irqfn != default_irqfn)
+-		csr_set(CSR_MIE, MIP_MEIP);
++	csr_set(CSR_MIE, MIP_MEIP);
+ 
+ 	return 0;
+ }
+@@ -47,8 +46,7 @@ void sbi_irqchip_exit(struct sbi_scratch *scratch)
+ {
+ 	const struct sbi_platform *plat = sbi_platform_ptr(scratch);
+ 
+-	if (ext_irqfn != default_irqfn)
+-		csr_clear(CSR_MIE, MIP_MEIP);
++	csr_clear(CSR_MIE, MIP_MEIP);
+ 
+ 	sbi_platform_irqchip_exit(plat);
+ }