diff --git a/JOURNAL.md b/JOURNAL.md
index 6ed6ce6..12fc4b4 100644
--- a/JOURNAL.md
+++ b/JOURNAL.md
@@ -2399,3 +2399,41 @@ puts the hang place at some point in between the check and the `pr_info()` call.
 If this is a problem on the OpenSBI side, we can bisect the code to find out
 where the problem was introduced. But first, I would have to try OpenSBI 1.4 and
 ensure we can reproduce it.
+
+Okay so with OpenSBI 1.4 we have a hang in the same place.
+
+Lets compare the domain regions:
+
+With OpenSBI 1.4 `fpga/alveo_ox`:
+
+    Domain0 Region00          : 0x0000000040000000-0x0000000040000fff M: (I,R,W) S/U: (R,W)
+    Domain0 Region01          : 0x0000000080040000-0x000000008004ffff M: (R,W) S/U: ()
+    Domain0 Region02          : 0x0000000080000000-0x000000008003ffff M: (R,X) S/U: ()
+    Domain0 Region03          : 0x0000000000000000-0xffffffffffffffff M: () S/U: (R,W,X)
+    Domain0 Next Address      : 0x0000000080200000
+    Domain0 Next Arg1         : 0x0000000080017000
+
+With OpenSBI 1.4 `generic`:
+
+    Domain0 Region00          : 0x0000000040001000-0x0000000040001fff M: (I,R,W) S/U: (R,W)
+    Domain0 Region01          : 0x0000000080040000-0x000000008005ffff M: (R,W) S/U: ()
+    Domain0 Region02          : 0x0000000080000000-0x000000008003ffff M: (R,X) S/U: ()
+    Domain0 Region03          : 0x0000000040800000-0x0000000040bfffff M: (I,R,W) S/U: (R,W)
+    Domain0 Region04          : 0x0000000000000000-0xffffffffffffffff M: () S/U: (R,W,X)
+    Domain0 Next Address      : 0x0000000080200000
+    Domain0 Next Arg1         : 0x0000000080100000
+
+With OpenSBI 1.5 `generic`:
+
+    Domain0 Region00          : 0x0000000040001000-0x0000000040001fff M: (I,R,W) S/U: (R,W)
+    Domain0 Region01          : 0x0000000080040000-0x000000008005ffff M: (R,W) S/U: ()
+    Domain0 Region02          : 0x0000000080000000-0x000000008003ffff M: (R,X) S/U: ()
+    Domain0 Region03          : 0x0000000040800000-0x0000000040bfffff M: (I,R,W) S/U: (R,W)
+    Domain0 Region04          : 0x0000000000000000-0xffffffffffffffff M: () S/U: (R,W,X)
+    Domain0 Next Address      : 0x0000000080200000
+    Domain0 Next Arg1         : 0x0000000080100000
+
+So we have several changes.
+
+First, the PLIC has a new memory map. Let's comment it out in the device tree,
+and see what happens.
diff --git a/ox-plic.dts b/ox-plic.dts
index 11f95b5..0f41ba0 100644
--- a/ox-plic.dts
+++ b/ox-plic.dts
@@ -132,8 +132,8 @@
 		uart_testing: serial@40003000 {
 			compatible = "ns16550";
 			reg = <0x0 0x40003000 0x0 0x1000>;
-			interrupts = <1>; /* Output interrupt 1 */
-			interrupt-parent = <&PLIC>;
+//			interrupts = <1>; /* Output interrupt 1 */
+//			interrupt-parent = <&PLIC>;
 			reg-shift = <2>;
 			clock-frequency = <50000000>;
 			current-speed = <115200>;
@@ -184,37 +184,37 @@
 
 		/* Platform-Level Interrupt Controller: Delivers interrupts to
 		 * HARTs. */
-		PLIC: plic@40800000 {
-			compatible = "riscv,plic0";
-			interrupt-controller; /* Receives interrupts */
-			#address-cells = <0>;
-			#interrupt-cells = <1>;
-			/* Sends interrupts to HART interrupt controllers */
-
-			/*
-			 * From: linux-6.6.1/arch/riscv/include/asm/csr.h
-			 *
-			 * Interrupt causes (minus the high bit)
-			 * #define IRQ_S_SOFT      1
-			 * #define IRQ_VS_SOFT     2
-			 * #define IRQ_M_SOFT      3
-			 * #define IRQ_S_TIMER     5
-			 * #define IRQ_VS_TIMER    6
-			 * #define IRQ_M_TIMER     7
-			 * #define IRQ_S_EXT       9
-			 * #define IRQ_VS_EXT      10
-			 * #define IRQ_M_EXT       11
-			 * #define IRQ_S_GEXT      12
-			 * #define IRQ_PMU_OVF     13
-			 * #define IRQ_LOCAL_MAX   (IRQ_PMU_OVF + 1)
-			 * #define IRQ_LOCAL_MASK  GENMASK((IRQ_LOCAL_MAX - 1), 0)
-			 */
-			interrupts-extended = <&HLIC0 11>, <&HLIC0 9>;
-			reg = < 0x0 0x40800000 0x0 0x00400000>;
-			riscv,ndev = <3>;
-			//riscv,max-priority = <0x7>;
-			phandle = <0x3>;
-		};
+//		PLIC: plic@40800000 {
+//			compatible = "riscv,plic0";
+//			interrupt-controller; /* Receives interrupts */
+//			#address-cells = <0>;
+//			#interrupt-cells = <1>;
+//			/* Sends interrupts to HART interrupt controllers */
+//
+//			/*
+//			 * From: linux-6.6.1/arch/riscv/include/asm/csr.h
+//			 *
+//			 * Interrupt causes (minus the high bit)
+//			 * #define IRQ_S_SOFT      1
+//			 * #define IRQ_VS_SOFT     2
+//			 * #define IRQ_M_SOFT      3
+//			 * #define IRQ_S_TIMER     5
+//			 * #define IRQ_VS_TIMER    6
+//			 * #define IRQ_M_TIMER     7
+//			 * #define IRQ_S_EXT       9
+//			 * #define IRQ_VS_EXT      10
+//			 * #define IRQ_M_EXT       11
+//			 * #define IRQ_S_GEXT      12
+//			 * #define IRQ_PMU_OVF     13
+//			 * #define IRQ_LOCAL_MAX   (IRQ_PMU_OVF + 1)
+//			 * #define IRQ_LOCAL_MASK  GENMASK((IRQ_LOCAL_MAX - 1), 0)
+//			 */
+//			interrupts-extended = <&HLIC0 11>, <&HLIC0 9>;
+//			reg = < 0x0 0x40800000 0x0 0x00400000>;
+//			riscv,ndev = <3>;
+//			//riscv,max-priority = <0x7>;
+//			phandle = <0x3>;
+//		};
 		/* Core Local Interruptor: It directly connects to the timer and
 		 * inter-processor interrupt lines of various HARTs (or CPUs) so
 		 * RISC-V per-HART (or per-CPU) local interrupt controller is