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Dump more registers in PLIC test

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This commit is contained in:
Rodrigo Arias Mallo 2024-08-21 09:44:53 +02:00
parent fd2b766760
commit baf45e6749
1 changed files with 28 additions and 28 deletions
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56
opensbi-test-plic.patch
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@ -1,5 +1,5 @@
diff --git a/lib/sbi/sbi_irqchip.c b/lib/sbi/sbi_irqchip.c
index 0ae604a..44601a4 100644
index 0ae604a..a3df88c 100644
--- a/lib/sbi/sbi_irqchip.c
+++ b/lib/sbi/sbi_irqchip.c
@@ -9,6 +9,9 @@
@ -61,6 +61,27 @@ index 0ae604a..44601a4 100644
+#define MSTATUS_MPP_MASK (3 << 11)
+#define MSTATUS_MPP_SUPERVISOR (1 << 11)
+
+static void dumpregs(void)
+{
+ char *prefix = "\t";
+ char *suffix = "\t";
+ sbi_printf("Registers:\n");
+ sbi_printf("%sMIE%s: 0x%" PRILX "\n",
+ prefix, suffix, csr_read(CSR_MIE));
+ sbi_printf("%sMIP%s: 0x%" PRILX "\n",
+ prefix, suffix, csr_read(CSR_MIP));
+ sbi_printf("%sMSTATUS%s: 0x%" PRILX "\n",
+ prefix, suffix, csr_read(CSR_MSTATUS));
+ sbi_printf("%sMIDELEG%s: 0x%" PRILX "\n",
+ prefix, suffix, csr_read(CSR_MIDELEG));
+ sbi_printf("%sSIE%s: 0x%" PRILX "\n",
+ prefix, suffix, csr_read(CSR_SIE));
+ sbi_printf("%sSIP%s: 0x%" PRILX "\n",
+ prefix, suffix, csr_read(CSR_SIP));
+ sbi_printf("%sSSTATUS%s: 0x%" PRILX "\n",
+ prefix, suffix, csr_read(CSR_SSTATUS));
+}
+
+static void __attribute__((optimize("O0"))) switch_to_supervisor_mode(int (*target_address)(void))
+{
+ unsigned long mstatus;
@ -83,10 +104,12 @@ index 0ae604a..44601a4 100644
+
+static int supervisor_mode_code(void)
+{
+ sbi_printf("Hello from supervisor, waiting for interrupt\n");
+ sbi_printf("Hello from supervisor\n");
+ sbi_printf("Waiting for interrupt...\n");
+ int i = 0;
+ char *s = "-\\|/";
+ while (1) {
+ for (volatile unsigned long j = 0; j < 100000; j++);
+ sbi_printf("\r%c", s[i++]);
+ if (i >= 4)
+ i = 0;
@ -97,8 +120,6 @@ index 0ae604a..44601a4 100644
+
+static void do_plic_test(void)
+{
+ char *prefix = "\t";
+ char *suffix = "\t";
+ sbi_printf("--- TESTING PLIC ---\n");
+
+ volatile unsigned long *mtime = (unsigned long *)(AUX_TIMER_BASE + MTIME_OFFSET);
@ -108,12 +129,6 @@ index 0ae604a..44601a4 100644
+ *mtimecmp = 0xffffffffUL;
+ sbi_printf("Timer interrupt disabled\n");
+
+ sbi_printf("%sSIE%s: 0x%" PRILX "\n",
+ prefix, suffix, csr_read(CSR_SIE));
+ sbi_printf("%sSSTATUS%s: 0x%" PRILX "\n",
+ prefix, suffix, csr_read(CSR_SSTATUS));
+ sbi_printf("%sMIDELEG%s: 0x%" PRILX "\n",
+ prefix, suffix, csr_read(CSR_MIDELEG));
+
+ /* Enable supervisor interrupt delegation */
+ csr_set(CSR_SIE, SIE_SEIE); // Enable supervisor external interrupts
@ -121,12 +136,7 @@ index 0ae604a..44601a4 100644
+ csr_set(CSR_MIDELEG, MIDELEG_SEIE); // Delegate machine interrupts to supervisor mode
+ sbi_printf("Enabled supervisor delegation:\n");
+
+ sbi_printf("%sSIE%s: 0x%" PRILX "\n",
+ prefix, suffix, csr_read(CSR_SIE));
+ sbi_printf("%sSSTATUS%s: 0x%" PRILX "\n",
+ prefix, suffix, csr_read(CSR_SSTATUS));
+ sbi_printf("%sMIDELEG%s: 0x%" PRILX "\n",
+ prefix, suffix, csr_read(CSR_MIDELEG));
+ dumpregs();
+
+ /* Configure PLIC aux timer input */
+ volatile unsigned *plic_priority = (unsigned *)(PLIC_BASE + PLIC_PRIORITY_OFFSET + PLIC_TIMER_PORT * 4);
@ -139,21 +149,9 @@ index 0ae604a..44601a4 100644
+
+ sbi_printf("Timer enabled in PLIC\n");
+
+// sbi_printf("%sMIE%s: 0x%" PRILX "\n",
+// prefix, suffix, csr_read(CSR_MIE));
+// sbi_printf("%sMSTATUS%s: 0x%" PRILX "\n",
+// prefix, suffix, csr_read(CSR_MSTATUS));
+//
+// /* Enable external timer interrupts */
+// csr_set(CSR_MIE, MIE_MEIE); /* Needed? */
+// csr_set(CSR_MSTATUS, MSTATUS_MIE); /* Needed? */
+//
+// sbi_printf("External timer interrupts enabled in machine mode\n");
+//
+// sbi_printf("%sMIE%s: 0x%" PRILX "\n",
+// prefix, suffix, csr_read(CSR_MIE));
+// sbi_printf("%sMSTATUS%s: 0x%" PRILX "\n",
+// prefix, suffix, csr_read(CSR_MSTATUS));
+
+ /* Enable timer interrupt */
+ *mtimecmp = *mtime + 10000;
@ -161,6 +159,8 @@ index 0ae604a..44601a4 100644
+ sbi_printf("Timer alarm programmed\n");
+ sbi_printf("Switching to supervisor\n");
+
+ dumpregs();
+
+ // Switch to supervisor mode and execute supervisor_mode_code
+ switch_to_supervisor_mode(&supervisor_mode_code);
+