diff --git a/overlay.nix b/overlay.nix
index 2b32356..8527ad1 100644
--- a/overlay.nix
+++ b/overlay.nix
@@ -45,8 +45,8 @@ final: prev:
     name = "sa-fpga-tests";
     src = builtins.fetchGit {
       url = "git@gitlab-internal.bsc.es:hwdesign/rtl/core-tile/sa-fpga.git";
-      rev = "afe0372413a94fff279ca5d5002c3e999ac8defb";
-      ref = "ft/sv_eirq";
+      rev = "720be4f1f5dd0ef963135992578be2ab55fb5537";
+      ref = "main";
     };
     dontConfigure = true;
     patches = [
@@ -54,6 +54,7 @@ final: prev:
       #./patches/sa-fpga-text-address.patch
       ./patches/sa-fpga-uart.patch
       ./patches/sa-fpga-plic-registers.patch
+      ./patches/sa-fpga-add-plic-claim-test.patch
     ];
     buildPhase = ''
       cd fpga_core_bridge/simulator/tests/c_tests/
diff --git a/patches/sa-fpga-add-plic-claim-test.patch b/patches/sa-fpga-add-plic-claim-test.patch
new file mode 100644
index 0000000..b9b6cb4
--- /dev/null
+++ b/patches/sa-fpga-add-plic-claim-test.patch
@@ -0,0 +1,92 @@
+commit 1a2c5f12e7676930123cfe7853f1805cf3680c25
+Author: Rodrigo Arias Mallo <rodrigo.arias@bsc.es>
+Date:   Tue Oct 1 12:59:38 2024 +0200
+
+    Add claim test
+
+diff --git a/fpga_core_bridge/simulator/tests/c_tests/Makefile b/fpga_core_bridge/simulator/tests/c_tests/Makefile
+index f744131..91d61b6 100644
+--- a/fpga_core_bridge/simulator/tests/c_tests/Makefile
++++ b/fpga_core_bridge/simulator/tests/c_tests/Makefile
+@@ -23,6 +23,7 @@ bmarks = \
+ 	plic \
+ 	plic_supervisor \
+ 	plic_threshold \
++	plic_claim \
+ 	clint_supervisor \
+ 	uart
+ 
+diff --git a/fpga_core_bridge/simulator/tests/c_tests/plic_claim/plic_claim.c b/fpga_core_bridge/simulator/tests/c_tests/plic_claim/plic_claim.c
+new file mode 100644
+index 0000000..352adb9
+--- /dev/null
++++ b/fpga_core_bridge/simulator/tests/c_tests/plic_claim/plic_claim.c
+@@ -0,0 +1,68 @@
++#include "util.h"
++
++#define PLIC_BASE 0x40800000
++
++int main(void)
++{
++	uart_init();
++
++	/* This test requires the auxiliar timer to cause a pending
++	 * interrupt in the source 4. All the other pending bits must be
++	 * zero. */
++
++	uint32_t src = 4;
++	uint32_t mask = 1 << src;
++
++	/* 0x001000: Interrupt Source #0 to #31 Pending Bits */
++	volatile uint32_t *pending = PLIC_BASE + 0x001000;
++
++	/* Manually enable the pending register on both timer and serial */
++	*pending = (1<<4) | (1<<1);
++
++	uint32_t p;
++	/* Wait for a interrupt on the serial line */
++	while ((p = *pending) != (1<<4) | (1<<1)) {
++		printf("waiting, pending=");
++		printhex(p);
++		printf("\n");
++	}
++
++	/* 0x002080: Interrupt Source #0 to #31 Enable Bits on context 1 */
++	volatile uint32_t *enable = PLIC_BASE + 0x002080;
++	*enable = (1<<4) | (1<<1); /* Enable source 4 (aux timer) and 1
++	(serial) */
++
++	/* 0x000004: Interrupt source 1 priority */
++	/* 0x000008: Interrupt source 2 priority */
++	/* 0x00000c: Interrupt source 3 priority */
++	/* 0x000010: Interrupt source 4 priority */
++	for (uint32_t i = 1; i <= 4; i++) {
++		volatile uint32_t *priority = PLIC_BASE + i * 4;
++		*priority = 1; /* Make priority larger than threshold */
++	}
++
++	/* 0x201000: Priority threshold for context 1 */
++	volatile uint32_t *threshold = PLIC_BASE + 0x201000;
++	*threshold = 0; /* Make threshold small */
++
++	/* Now the context 1 must be receiving interrupts from the aux
++	 * timer. Let's try to claim the interrupt. */
++
++	/* Read claim */
++
++	/* 0x201004: Interrupt Claim Process for context 1 */
++	volatile uint32_t *claim = PLIC_BASE + 0x201004;
++	while (1) {
++		uint32_t c = *claim;
++		if (c == src)
++			break;
++		printf("ERROR: unexpected claim found, expecting 4: ");
++		printhex(c);
++		printf("\n");
++	}
++
++	while (1)
++		printf("SUCCESS: Claim test succeeded\n");
++
++	return 0;
++}