Update journal

JOURNAL.md

@@ -3624,3 +3624,118 @@ potential errors:
 While the bitstream with the potential fixes for the supervisor interrupts is
 not available, I'll try to automate the testing by creating a pipeline that
 automatically runs the tests in an FPGA.
+
+## 2024-08-29
+
+The `plic_supervisor` baremetal test seems to be working with bitstream
+`ox_u55c_450d0ff0_fix_delegation_v2.bit`. Here is the output with registers
+dumped:
+
+    Set timer interval.
+    Registers:
+        MIE: 0000000000000200
+        MIP: 0000000000000280
+    MSTATUS: 8000000a00006002
+    MIDELEG: 0000000000000200
+        SIE: 0000000000000200
+        SIP: 0000000000000200
+    SSTATUS: 8000000200006002
+
+    Jumping to supervisor mode...
+
+    Supervisor Trap Entry Reached
+    Cause: 8000000000000009 EPC: 000000008000111a
+    Hi from PLIC Interrupt Service Routine!
+    Claim interrupt: 0000000000000004
+    Set timer interval.
+
+
+    Supervisor Trap Entry Reached
+    Cause: 8000000000000009 EPC: 0000000080001e88
+    Hi from PLIC Interrupt Service Routine!
+    Claim interrupt: 0000000000000004
+    Set timer interval.
+
+In our OpenSBI test however:
+
+    OpenSBI v1.5
+       ____                    _____ ____ _____
+      / __ \                  / ____|  _ \_   _|
+     | |  | |_ __   ___ _ __ | (___ | |_) || |
+     | |  | | '_ \ / _ \ '_ \ \___ \|  _ < | |
+     | |__| | |_) |  __/ | | |____) | |_) || |_
+      \____/| .__/ \___|_| |_|_____/|____/_____|
+            | |
+            |_|
+    
+    --- TESTING PLIC ---
+    Timer interrupt disabled
+    Enabled supervisor delegation:
+    Registers:
+    	MIE	: 0x0000000000000200
+    	MIP	: 0x0000000000000080
+    	MSTATUS	: 0x8000000a00006082
+    	MIDELEG	: 0x0000000000000222
+    	SIE	: 0x0000000000000200
+    	SIP	: 0x0000000000000000
+    	SSTATUS	: 0x8000000200006002
+    Enabling timer in PLIC
+    Pending: 16
+    Claim: 4
+    Pending: 0
+    Clearing MIP
+    Switching to supervisor
+    Registers:
+    	MIE	: 0x0000000000000200
+    	MIP	: 0x0000000000000080
+    	MSTATUS	: 0x8000000a00006082
+    	MIDELEG	: 0x0000000000000222
+    	SIE	: 0x0000000000000200
+    	SIP	: 0x0000000000000000
+    	SSTATUS	: 0x8000000200006002
+    Hello from supervisor
+    Registers:
+    	SIE	: 0x0000000000000200
+    	SIP	: 0x0000000000000000
+    	SSTATUS	: 0x8000000200006002
+    Timer alarm programmed
+    Waiting for interrupt...
+
+Here are closer together:
+
+    Baremetal:
+        MIE: 0000000000000200
+        MIP: 0000000000000280
+    MSTATUS: 8000000a00006002
+    MIDELEG: 0000000000000200
+        SIE: 0000000000000200
+        SIP: 0000000000000200
+    SSTATUS: 8000000200006002
+    ---------------------------------
+    OpenSBI:
+        MIE: 0000000000000200
+        MIP: 0000000000000080 *
+    MSTATUS: 8000000a00006082 *
+    MIDELEG: 0000000000000222 *
+        SIE: 0000000000000200
+        SIP: 0000000000000000 *
+    SSTATUS: 8000000200006002
+
+In the baremetal test, the interrupts are already pending before jumping to
+supervisor.
+
+Let's try following all the steps exactly the same in OpenSBI.
+
+The supervisor trap address hold the proper function.
+
+The problem seems to be that the offsets I was using for the auxiliar timer were
+not correct:
+
+    -#define PLIC_ENABLE_OFFSET      0x2000UL
+    -#define PLIC_THRESHOLD_OFFSET   0x200000UL
+    -#define PLIC_CLAIM_OFFSET       0x200004UL
+    +#define PLIC_ENABLE_OFFSET      0x2080UL
+    +#define PLIC_THRESHOLD_OFFSET   0x201000UL
+    +#define PLIC_CLAIM_OFFSET       0x201004UL
+
+This seems to be required now as we have two contexts. The test is working now.