diff --git a/lagarto-ox.nix b/lagarto-ox.nix
index 37543d2..71f0e49 100644
--- a/lagarto-ox.nix
+++ b/lagarto-ox.nix
@@ -255,16 +255,17 @@
     '';
 
     opensbi = prev.opensbi.overrideAttrs (old: rec {
-      version = "1.4";
-      src = prev.fetchFromGitHub {
-        owner = "riscv-software-src";
-        repo = "opensbi";
-        rev = "v${version}";
-        hash = "sha256-T8ZeAzjM9aeTXitjE7s+m+jjGGtDo2jK1qO5EuKiVLU=";
-      };
+      #version = "1.4";
+      #src = prev.fetchFromGitHub {
+      #  owner = "riscv-software-src";
+      #  repo = "opensbi";
+      #  rev = "v${version}";
+      #  hash = "sha256-T8ZeAzjM9aeTXitjE7s+m+jjGGtDo2jK1qO5EuKiVLU=";
+      #};
       #NIX_DEBUG=5;
       makeFlags = [
-        "PLATFORM=fpga/ox_alveo"
+        "PLATFORM=fpga/openpiton"
+        #"PLATFORM=fpga/ox_alveo"
         #"CONFIG_SBI_ECALL_RFENCE=n"
         #"PLATFORM_RISCV_ISA=rv64imafd" # No compressed instructions
         #"PLATFORM_RISCV_ISA=rv64g" # No compressed instructions
@@ -272,7 +273,7 @@
         "FW_PAYLOAD_PATH=${final.uboot}/u-boot.bin"
         "FW_FDT_PATH=${final.ox-dtb}"
       ];
-      patches = [ ./ox-alveo-platform-plic.patch ];
+      patches = [ ./opensbi-lagarto-ox.patch ];
     });
 #    opensbi = prev.opensbi.overrideAttrs (old: {
 #      #NIX_DEBUG=5;
diff --git a/opensbi-lagarto-ox.patch b/opensbi-lagarto-ox.patch
new file mode 100644
index 0000000..d3dfce8
--- /dev/null
+++ b/opensbi-lagarto-ox.patch
@@ -0,0 +1,26 @@
+diff --git a/platform/fpga/openpiton/platform.c b/platform/fpga/openpiton/platform.c
+index 2317a89..4a83ca9 100644
+--- a/platform/fpga/openpiton/platform.c
++++ b/platform/fpga/openpiton/platform.c
+@@ -17,17 +17,17 @@
+ #include <sbi_utils/serial/uart8250.h>
+ #include <sbi_utils/timer/aclint_mtimer.h>
+ 
+-#define OPENPITON_DEFAULT_UART_ADDR		0xfff0c2c000
+-#define OPENPITON_DEFAULT_UART_FREQ		60000000
++#define OPENPITON_DEFAULT_UART_ADDR		0x40001000
++#define OPENPITON_DEFAULT_UART_FREQ		50000000
+ #define OPENPITON_DEFAULT_UART_BAUDRATE		115200
+ #define OPENPITON_DEFAULT_UART_REG_SHIFT	0
+ #define OPENPITON_DEFAULT_UART_REG_WIDTH	1
+-#define OPENPITON_DEFAULT_UART_REG_OFFSET	0
++#define OPENPITON_DEFAULT_UART_REG_OFFSET	0x1000
+ #define OPENPITON_DEFAULT_PLIC_ADDR		0xfff1100000
+ #define OPENPITON_DEFAULT_PLIC_SIZE		(0x200000 + \
+ 				(OPENPITON_DEFAULT_HART_COUNT * 0x1000))
+ #define OPENPITON_DEFAULT_PLIC_NUM_SOURCES	2
+-#define OPENPITON_DEFAULT_HART_COUNT		3
++#define OPENPITON_DEFAULT_HART_COUNT		1
+ #define OPENPITON_DEFAULT_CLINT_ADDR		0xfff1020000
+ #define OPENPITON_DEFAULT_ACLINT_MTIMER_FREQ	1000000
+ #define OPENPITON_DEFAULT_ACLINT_MSWI_ADDR	\