Set stvec to zero

This commit is contained in:
Rodrigo Arias Mallo 2024-08-02 16:11:52 +02:00
parent 98f794e52d
commit 91d3e9b163
2 changed files with 55 additions and 4 deletions

View File

@ -3410,3 +3410,53 @@ supervisor registers, to check they have the proper values.
sstatus : 0x8000000200006002
Now I can see the external interrupt in supervisor arriving to the SIP.
Let's try to cause an interrupt with the normal CLINT:
`define CLINT_XBAR_ID 3
`define CLINT_BASE_ADDR 64'h0000_0000_4010_0000
`define CLINT_END_ADDR 64'h0000_0000_4010_FFFF
`define AUX_TIMER_XBAR_ID 2
`define AUX_TIMER_BASE_ADDR 64'h0000_0000_4001_0000 // Need to be this space because we use a clint as aux timer
`define AUX_TIMER_END_ADDR 64'h0000_0000_4001_FFFF
=> exception sregs
stvec : 0x00000000af6f4400
sie : 0x0000000000000000
sip : 0x0000000000000000
sstatus : 0x8000000200006000
=> exception enable
=> exception sregs
stvec : 0x00000000af6f4400
sie : 0x0000000000000222
sip : 0x0000000000000000
sstatus : 0x8000000200006002
=> md 0x4010bff8 # Show normal CLINT mtime value
4010bff8: 00c8159b ....
=> md 0x4010bff8 # Show normal CLINT mtime value
4010bff8: 00c84453 SD..
=> md 0x4010bff8 # Show normal CLINT mtime value
4010bff8: 00c865b5 .e..
=> md 0x40104000 # Show normal CLINT mtimecmp value
40104000: 00000000 ....
=> mw 0x40104000 aaaaaaaa # Disable interrupt for CLINT
=> md 0x40104000 # Show normal CLINT mtimecmp value
40104000: aaaaaaaa ....
=> exception sregs
stvec : 0x00000000af6f4400
sie : 0x0000000000000222
sip : 0x0000000000000000
sstatus : 0x8000000200006002
=> mw 0x40104000 0 # Enable interrupt for CLINT
=> exception sregs
stvec : 0x00000000af6f4400
sie : 0x0000000000000222
sip : 0x0000000000000000 <-- nothing here
sstatus : 0x8000000200006002
=> md 0x40104000 # Show normal CLINT mtimecmp value
40104000: 00000000
No interrupts seem to arrive at the SIP register.
Let's set the stvec to zero, so it causes a machine exception.

View File

@ -1,8 +1,8 @@
diff --git a/cmd/riscv/exception.c b/cmd/riscv/exception.c
index f38f454a0b..9de4effe47 100644
index f38f454a0b..9bc554b0aa 100644
--- a/cmd/riscv/exception.c
+++ b/cmd/riscv/exception.c
@@ -56,6 +56,40 @@ static int do_undefined(struct cmd_tbl *cmdtp, int flag, int argc,
@@ -56,6 +56,41 @@ static int do_undefined(struct cmd_tbl *cmdtp, int flag, int argc,
return CMD_RET_FAILURE;
}
@ -33,6 +33,7 @@ index f38f454a0b..9de4effe47 100644
+ asm volatile (
+ "csrsi sstatus, 2\n" /* Enable SIE */
+ "csrs sie, %0\n" /* Enable selected interrupts */
+ "csrwi stvec, 0\n" /* Redirect trap handler to NULL */
+ : /* no output */
+ : "r" (which)
+ );
@ -43,7 +44,7 @@ index f38f454a0b..9de4effe47 100644
static struct cmd_tbl cmd_sub[] = {
U_BOOT_CMD_MKENT(compressed, CONFIG_SYS_MAXARGS, 1, do_compressed,
"", ""),
@@ -67,6 +101,10 @@ static struct cmd_tbl cmd_sub[] = {
@@ -67,6 +102,10 @@ static struct cmd_tbl cmd_sub[] = {
"", ""),
U_BOOT_CMD_MKENT(undefined, CONFIG_SYS_MAXARGS, 1, do_undefined,
"", ""),
@ -54,7 +55,7 @@ index f38f454a0b..9de4effe47 100644
};
static char exception_help_text[] =
@@ -77,6 +115,8 @@ static char exception_help_text[] =
@@ -77,6 +116,8 @@ static char exception_help_text[] =
" ialign16 - 16 bit aligned instruction\n"
" undefined - illegal instruction\n"
" unaligned - load address misaligned\n"