Add FPGA baremetal tests

JOURNAL.md

@@ -3461,7 +3461,7 @@ No interrupts seem to arrive at the SIP register.
 
 Let's set the stvec to zero, so it causes a machine exception.
 
-# 2024-08-21
+## 2024-08-21
 
 I tried with the new bitstream (`ox_u55c_46619ef4.bit`) setting the stvec to zero
 and I can see the OpenSBI handler stopping, probably due to the jump to zero
@@ -3589,3 +3589,21 @@ interrupt over to supervisor.
 Let's dump the machine registers too.
 
 Let's also disable the MEIE bit in MIE register.
+
+## 2024-08-22
+
+I'm unable to delegate the external interrupt to supervisor. It is always
+intercepted by OpenSBI in machine mode or nothing happens.
+
+I may still be missing some bit in some register that prevents the delegation
+from working. So I tried to run the bare metal tests, specifically
+`plic_supervisor` from here:
+
+    https://gitlab.bsc.es/hwdesign/rtl/core-tile/sa-fpga/-/blob/6547e63f3aed312a4c36f093b5e6421c7f1704f6/fpga_core_bridge/simulator/tests/c_tests/plic_supervisor/plic_supervisor_test.c
+
+But I'm not able to make them run. I added them to Nix and created a bootable
+image with objcopy, but nothing is displayed in the UART. I also tried to patch
+the .text.init address to 0x100 without luck.
+
+I think the next experiment I will do is try to port the baremetal tests to
+something I can load at `0x8000_0000`

overlay.nix

@@ -73,4 +73,37 @@ final: prev:
     url = "git@bscpm03.bsc.es:rarias/bitstreams.git";
     rev = "ad901b0c21ffbdb310ff1dfb269f169f6ac6bde6";
   };
+
+  # Baremetal tests for standalone FPGA
+  sa-fpga-tests = prev.pkgsStatic.stdenv.mkDerivation {
+    name = "sa-fpga-tests";
+    src = builtins.fetchGit {
+      url = "git@gitlab-internal.bsc.es:hwdesign/rtl/core-tile/sa-fpga.git";
+      rev = "6547e63f3aed312a4c36f093b5e6421c7f1704f6";
+      ref = "ni/supervisor_tests";
+    };
+    dontConfigure = true;
+    patches = [
+      #./sa-fpga-crt.patch
+      #./sa-fpga-text-address.patch
+    ];
+    buildPhase = ''
+      cd fpga_core_bridge/simulator/tests/c_tests/
+      make RISCV_PREFIX=riscv64-unknown-linux-musl-
+
+      # Generate binary images to be loaded in memory
+      for f in *.riscv; do
+        # Don't copy 0x40000000 section
+        $OBJCOPY -R .tohost -O binary $f $f.bin
+      done
+    '';
+    installPhase = ''
+      ls -lah
+      make install install_dir=$out
+      cp -a *.bin $out
+    '';
+    dontFixup = true;
+    hardeningDisable = [ "all" ];
+  };
+
 }

sa-fpga-crt.patch

@@ -0,0 +1,15 @@
+diff --git a/fpga_core_bridge/simulator/tests/c_tests/common/crt.S b/fpga_core_bridge/simulator/tests/c_tests/common/crt.S
+index 3f5bb2c..bd738b1 100644
+--- a/fpga_core_bridge/simulator/tests/c_tests/common/crt.S
++++ b/fpga_core_bridge/simulator/tests/c_tests/common/crt.S
+@@ -59,10 +59,6 @@ _start:
+ #else
+   bltz t0, 1f
+ #endif
+-2:
+-  li a0, 1
+-  sw a0, tohost, t0
+-  j 2b
+ 1:
+ 
+ #ifdef __riscv_flen

sa-fpga-text-address.patch

@@ -0,0 +1,13 @@
+diff --git a/fpga_core_bridge/simulator/tests/c_tests/common/test.ld b/fpga_core_bridge/simulator/tests/c_tests/common/test.ld
+index 8321d86..f83a9ee 100644
+--- a/fpga_core_bridge/simulator/tests/c_tests/common/test.ld
++++ b/fpga_core_bridge/simulator/tests/c_tests/common/test.ld
+@@ -26,7 +26,7 @@ SECTIONS
+   .tohost : { *(.tohost) }
+
+   /* text: test code section */
+-  . = 0x80000000;
++  . = 0x20020000;
+   .text.init : { *(.text.init) }
+
+   . = ALIGN(0x1000);