rarias/nixos-riscv
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Simplify, correct and comment DTS

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Disable unused devices and try to fix the interrupt connections. The
compiler dtc doesn't report any warning now.
This commit is contained in:
Rodrigo Arias 2024-07-01 11:25:59 +02:00
parent 33b227f576
commit 763f053f01
1 changed files with 109 additions and 89 deletions
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198
ox-plic.dts
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@ -1,31 +1,42 @@
/dts-v1/; /dts-v1/;
/ { / {
#address-cells = <0x00000002>; #address-cells = <2>;
#size-cells = <0x00000002>; #size-cells = <2>; /* 64 bits memory addresses */
compatible = "riscv,rv64i"; compatible = "riscv,rv64i";
model = "Barcelona Supercomputing Center - Lagarto Ox (NixOS)"; model = "Barcelona Supercomputing Center - Lagarto Ox (NixOS)";
chosen { chosen {
bootargs = "earlyprintk ignore_loglevel earlycon=sbi console=hvc0 root=/dev/pmem0p1 ro init=/bin/bash"; bootargs = "earlyprintk ignore_loglevel earlycon=sbi console=hvc0 root=/dev/pmem0p1 ro init=/bin/bash";
}; };
cpus { cpus {
#address-cells = <0x00000001>; #address-cells = <1>;
#size-cells = <0x00000000>; #size-cells = <0>;
timebase-frequency = <0x0000c350>; /* Timer */
timebase-frequency = <50000>; /* 50 kHz */
CPU0: cpu@0 { CPU0: cpu@0 {
clock-frequency = <0x02FAF080>; clock-frequency = <50000000>; /* 50 MHz */
device_type = "cpu"; device_type = "cpu";
reg = <0x00000000>; reg = <0>;
status = "okay"; status = "okay";
compatible = "riscv"; compatible = "riscv";
riscv,isa = "rv64imafd"; riscv,isa = "rv64imafd";
mmu-type = "riscv,sv39"; mmu-type = "riscv,sv39";
tlb-split; tlb-split;
phandle = <0x00000004>; phandle = <0x00000004>;
L3: interrupt-controller { /* Hart-Level Interrupt Controller: Every interrupt is
#interrupt-cells = <0x00000001>; * ultimately routed through a hart's HLIC before it
interrupt-controller; * interrupts that hart. */
HLIC0: interrupt-controller {
#interrupt-cells = <1>;
interrupt-controller; /* Receives interrupts */
compatible = "riscv,cpu-intc"; compatible = "riscv,cpu-intc";
phandle = <0x00000005>; phandle = <0x5>;
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
}; };
}; };
}; };
@ -39,29 +50,27 @@
*/ */
memory@80000000 { memory@80000000 {
device_type = "memory"; device_type = "memory";
reg = <0x00000000 0x80000000 0x00000000 0x7ff00000>; reg = <0x0 0x80000000 0x0 0x7ff00000>;
}; };
reserved-memory { reserved-memory {
#address-cells = <0x00000002>; #address-cells = <2>; /* Starting address and size */
#size-cells = <0x00000002>; #size-cells = <2>; /* 64 bits memory addresses */
ranges; ranges;
eth_pool: dma_pool@60000000 { eth_pool: dma_pool@60000000 {
reg = <0x00000000 0x60000000 0x00000000 0x10000000>; reg = <0x0 0x60000000 0x0 0x10000000>;
compatible = "shared-dma-pool"; compatible = "shared-dma-pool";
phandle = <0x00000001>;
}; };
onic_pool: dma_pool@70000000 { onic_pool: dma_pool@70000000 {
reg = <0x00000000 0x70000000 0x00000000 0x10000000>; reg = <0x0 0x70000000 0x0 0x10000000>;
compatible = "shared-dma-pool"; compatible = "shared-dma-pool";
phandle = <0x00000006>;
}; };
}; };
eth0_clk: eth0_clk { // eth0_clk: eth0_clk {
compatible = "fixed-clock"; // compatible = "fixed-clock";
#clock-cells = <0x00000000>; // #clock-cells = <0x00000000>;
clock-frequency = <0x09502f90>; // clock-frequency = <0x09502f90>;
phandle = <0x00000002>; // phandle = <0x00000002>;
}; // };
pmem@1bff00000 { pmem@1bff00000 {
/* volatile; This property indicates that this region is /* volatile; This property indicates that this region is
* actually backed by non-persistent memory. This lets the OS * actually backed by non-persistent memory. This lets the OS
@ -69,7 +78,7 @@
* data is made persistent after a write. */ * data is made persistent after a write. */
volatile; volatile;
compatible = "pmem-region"; compatible = "pmem-region";
reg = <0x00000001 0xbff00000 0x00000000 0xc0100000>; reg = <0x1 0xbff00000 0x0 0xc0100000>;
}; };
soc { soc {
#address-cells = <0x00000002>; #address-cells = <0x00000002>;
@ -78,76 +87,87 @@
ranges; ranges;
SERIAL: serial@40001000 { SERIAL: serial@40001000 {
compatible = "ns16550"; compatible = "ns16550";
reg = <0x0 0x40001000 0x0 0x00000100>; reg = <0x0 0x40001000 0x0 0x100>;
interrupts = <0>; interrupts = <0>; /* Output interrupt 0 */
/*port-number = <0>;*/ interrupt-parent = <&PLIC>;
reg-shift = <2>; reg-shift = <2>;
clock-frequency = <50000000>; clock-frequency = <50000000>;
current-speed = <115200>; current-speed = <115200>;
status = "okay"; status = "okay";
phandle = <0x00000007>;
}; };
ethernet0 {
xlnx,rxmem = <0x000005f2>; // ethernet0 {
carv,mtu = <0x000005dc>; // xlnx,rxmem = <0x000005f2>;
carv,no-mac; // carv,mtu = <0x000005dc>;
device_type = "network"; // carv,no-mac;
local-mac-address = [02 05 00 01 00 05]; // device_type = "network";
axistream-connected = <0x000000fe>; // local-mac-address = [02 05 00 01 00 05];
compatible = "xlnx,xxv-ethernet-1.0-carv"; // axistream-connected = <0x000000fe>;
memory-region = <&eth_pool>; // compatible = "xlnx,xxv-ethernet-1.0-carv";
}; // memory-region = <&eth_pool>;
dma@40400000 { // };
xlnx,include-dre; // dma@40400000 {
phandle = <0x000000fe>; // xlnx,include-dre;
#dma-cells = <0x00000001>; // phandle = <0x000000fe>;
compatible = "xlnx,axi-dma-1.00.a"; // #dma-cells = <0x00000001>;
clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", "m_axi_sg_aclk"; // compatible = "xlnx,axi-dma-1.00.a";
clocks = <&eth0_clk>, <&eth0_clk>, <&eth0_clk>, <&eth0_clk>; // clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", "m_axi_sg_aclk";
reg = <0x00000000 0x40400000 0x00000000 0x00400000>; // clocks = <&eth0_clk>, <&eth0_clk>, <&eth0_clk>, <&eth0_clk>;
interrupt-names = "mm2s_introut", "s2mm_introut"; // reg = <0x00000000 0x40400000 0x00000000 0x00400000>;
interrupt-parent = <&PLIC0>; // interrupt-names = "mm2s_introut", "s2mm_introut";
interrupts = <0x00000002 0x00000003>; // interrupt-parent = <&PLIC>;
xlnx,addrwidth = <0x00000028>; // interrupts = <2 3>;
xlnx,include-sg; // xlnx,addrwidth = <0x00000028>;
xlnx,sg-length-width = <0x00000017>; // xlnx,include-sg;
dma-channel@40400000 { // xlnx,sg-length-width = <0x00000017>;
compatible = "xlnx,axi-dma-mm2s-channel"; // dma-channel@40400000 {
dma-channels = <0x00000000>; // compatible = "xlnx,axi-dma-mm2s-channel";
interrupts = <0x00000002>; // dma-channels = <0x00000000>;
xlnx,datawidth = <0x00000040>; // interrupts = <0x00000002>;
xlnx,device-id = <0x00000000>; // xlnx,datawidth = <0x00000040>;
xlnx,include-dre; // xlnx,device-id = <0x00000000>;
}; // xlnx,include-dre;
dma-channel@40400030 { // };
compatible = "xlnx,axi-dma-s2mm-channel"; // dma-channel@40400030 {
dma-channels = <0x00000001>; // compatible = "xlnx,axi-dma-s2mm-channel";
interrupts = <0x00000003>; // dma-channels = <0x00000001>;
xlnx,datawidth = <0x00000040>; // interrupts = <0x00000003>;
xlnx,device-id = <0x00000000>; // xlnx,datawidth = <0x00000040>;
xlnx,include-dre; // xlnx,device-id = <0x00000000>;
}; // xlnx,include-dre;
}; // };
clint@40002000 { // };
reg-names = "control";
interrupts-extended = /* Platform-Level Interrupt Controller: Delivers interrupts to
<&CPU0 0x3>, <&CPU0 0x7>, * HARTs. */
<&L3 0x3>, <&L3 0x7>, PLIC: plic@40800000 {
<&onic_pool 0x3>, <&onic_pool 0x7>,
<&SERIAL 0x3>, <&SERIAL 0x7>;
compatible = "riscv,clint0";
#interrupt-cells = <0x00000001>;
reg = <0x00000000 0x40002000 0x00000000 0x000c0000>;
};
PLIC0: plic@40800000 {
#interrupt-cells = <1>;
compatible = "riscv,plic0"; compatible = "riscv,plic0";
interrupt-controller; interrupt-controller; /* Receives interrupts */
interrupts-extended = <&L3 3 &L3 7>; #interrupt-cells = <1>;
reg = < 0x00000000 0x40800000 0x00000000 0x00400000>; /* Sends interrupts to HART interrupt controllers */
riscv,ndev = <0x00000003>; interrupts-extended = <&HLIC0 3 &HLIC0 7>;
riscv,max-priority = <0x00000007>; reg = < 0x0 0x40800000 0x0 0x00400000>;
phandle = <0x00000003>; riscv,ndev = <0x3>;
riscv,max-priority = <0x7>;
phandle = <0x3>;
};
/* Core Local Interruptor: It directly connects to the timer and
* inter-processor interrupt lines of various HARTs (or CPUs) so
* RISC-V per-HART (or per-CPU) local interrupt controller is
* the parent interrupt controller for CLINT device. The clock
* frequency of CLINT is specified via "timebase-frequency" DT
* property of "/cpus" DT node. The "timebase-frequency" DT
* property is described in
* Documentation/devicetree/bindings/riscv/cpus.yaml
*/
timer@40002000 {
reg = <0x0 0x40002000 0x0 0x000c0000>;
reg-names = "control";
interrupts-extended = <&HLIC0 3>, <&HLIC0 7>;
/*<&CPU0 0x3>, <&CPU0 0x7>,*/
/*<&onic_pool 0x3>, <&onic_pool 0x7>,*/
/*<&SERIAL 0x3>, <&SERIAL 0x7>*/
compatible = "riscv,clint0";
}; };
}; };
}; };