From 6a57dd004fe09bbd86f1bb3c4da7dd341e00fd02 Mon Sep 17 00:00:00 2001 From: Rodrigo Arias Mallo Date: Fri, 12 Jul 2024 13:55:08 +0200 Subject: [PATCH] Switch to "riscv,aclint-mtimer" timer --- JOURNAL.md | 38 ++++++++++++++++++++++++++++++++++++++ opensbi-timer-debug.patch | 6 +++--- ox-plic.dts | 4 +++- 3 files changed, 44 insertions(+), 4 deletions(-) diff --git a/JOURNAL.md b/JOURNAL.md index 0c888da..9a5b9df 100644 --- a/JOURNAL.md +++ b/JOURNAL.md @@ -1674,3 +1674,41 @@ It seems that SiFive timer has a very long weird offset: We may want to use the ACLINT timer instead. Let's first see where the addresses lay in memory, and then use that to verify we change it to 0x0 and 0x8. + + GGGGGGGGG + OpenSBI v1.5 + ____ _____ ____ _____ + / __ \ / ____| _ \_ _| + | | | |_ __ ___ _ __ | (___ | |_) || | + | | | | '_ \ / _ \ '_ \ \___ \| _ < | | + | |__| | |_) | __/ | | |____) | |_) || |_ + \____/| .__/ \___|_| |_|_____/|____/_____| + | | + |_| + + sbi_timer_init: begins + sbi_timer_init: got Zicntr extension + fdt_timer_cold_init: pos = 0 + fdt_timer_cold_init: got match, name = riscv,clint0 + fdt_timer_cold_init: enabled + timer_mtimer_cold_init: begins, is_clint = 1 + timer_mtimer_cold_init: mtime_addr = 0x4000dff8 + timer_mtimer_cold_init: mtime_size = 0x000b4008 + timer_mtimer_cold_init: mtime_addr = 0x40006000 + timer_mtimer_cold_init: mtime_addr = 0x00007ff8 + fdt_timer_cold_init: drc->cold_init = -3 + fdt_timer_init: fdt_timer_cold_init failed (-3) + sbi_platform_timer: sbi_platform_timer_init failed (-3) + init_coldboot: timer init failed (error -3) + +Yeah, those addresses are not what we want. Based on the device tree, the clint +must be at 0x40002000, so they should be 40002000 and 40002008. Also I made some +typos in the printf command, this is the patch: + + + sbi_printf("timer_mtimer_cold_init: mtime_addr = 0x%08lx\n", mt->mtime_addr); + + sbi_printf("timer_mtimer_cold_init: mtime_size = 0x%08lx\n", mt->mtime_size); + + sbi_printf("timer_mtimer_cold_init: mtime_addr = 0x%08lx\n", mt->mtimecmp_addr); + + sbi_printf("timer_mtimer_cold_init: mtime_addr = 0x%08lx\n", mt->mtimecmp_size); + +So, let's fix the patch and switch to the "riscv,aclint-mtimer" timer, which +doesn't set any quirk or weird offset. diff --git a/opensbi-timer-debug.patch b/opensbi-timer-debug.patch index f2155f2..292e46c 100644 --- a/opensbi-timer-debug.patch +++ b/opensbi-timer-debug.patch @@ -99,7 +99,7 @@ index f468730..db20526 100644 + return rc; } diff --git a/lib/utils/timer/fdt_timer_mtimer.c b/lib/utils/timer/fdt_timer_mtimer.c -index 9e27e3a..fba48ca 100644 +index 9e27e3a..cef2ee6 100644 --- a/lib/utils/timer/fdt_timer_mtimer.c +++ b/lib/utils/timer/fdt_timer_mtimer.c @@ -8,6 +8,7 @@ @@ -149,8 +149,8 @@ index 9e27e3a..fba48ca 100644 + sbi_printf("timer_mtimer_cold_init: mtime_addr = 0x%08lx\n", mt->mtime_addr); + sbi_printf("timer_mtimer_cold_init: mtime_size = 0x%08lx\n", mt->mtime_size); -+ sbi_printf("timer_mtimer_cold_init: mtime_addr = 0x%08lx\n", mt->mtimecmp_addr); -+ sbi_printf("timer_mtimer_cold_init: mtime_addr = 0x%08lx\n", mt->mtimecmp_size); ++ sbi_printf("timer_mtimer_cold_init: mtimecmp_addr = 0x%08lx\n", mt->mtimecmp_addr); ++ sbi_printf("timer_mtimer_cold_init: mtimecmp_size = 0x%08lx\n", mt->mtimecmp_size); + /* Apply additional quirks */ if (quirks) { diff --git a/ox-plic.dts b/ox-plic.dts index 35cf1e2..1959cfb 100644 --- a/ox-plic.dts +++ b/ox-plic.dts @@ -234,7 +234,9 @@ /*<&CPU0 0x3>, <&CPU0 0x7>,*/ /*<&onic_pool 0x3>, <&onic_pool 0x7>,*/ /*<&SERIAL 0x3>, <&SERIAL 0x7>*/ - compatible = "riscv,clint0"; + + /* Allows using the "generic" platform in OpenSBI. */ + compatible = "riscv,aclint-mtimer"; }; /* Guesswork: There must be a timer at 0x40170000 as it is