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WIP: Test M and S ext interrupt

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This commit is contained in:
Rodrigo Arias 2024-07-03 20:39:17 +02:00
parent b1755354d0
commit 6531fd678c
1 changed files with 23 additions and 3 deletions
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26
ox-plic.dts
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@ -145,12 +145,32 @@
PLIC: plic@40800000 { PLIC: plic@40800000 {
compatible = "riscv,plic0"; compatible = "riscv,plic0";
interrupt-controller; /* Receives interrupts */ interrupt-controller; /* Receives interrupts */
#address-cells = <0>;
#interrupt-cells = <1>; #interrupt-cells = <1>;
/* Sends interrupts to HART interrupt controllers */ /* Sends interrupts to HART interrupt controllers */
interrupts-extended = <&HLIC0 2>;
/*
* From: linux-6.6.1/arch/riscv/include/asm/csr.h
*
* Interrupt causes (minus the high bit)
* #define IRQ_S_SOFT 1
* #define IRQ_VS_SOFT 2
* #define IRQ_M_SOFT 3
* #define IRQ_S_TIMER 5
* #define IRQ_VS_TIMER 6
* #define IRQ_M_TIMER 7
* #define IRQ_S_EXT 9
* #define IRQ_VS_EXT 10
* #define IRQ_M_EXT 11
* #define IRQ_S_GEXT 12
* #define IRQ_PMU_OVF 13
* #define IRQ_LOCAL_MAX (IRQ_PMU_OVF + 1)
* #define IRQ_LOCAL_MASK GENMASK((IRQ_LOCAL_MAX - 1), 0)
*/
interrupts-extended = <&HLIC0 9>, <&HLIC0 11>;
reg = < 0x0 0x40800000 0x0 0x00400000>; reg = < 0x0 0x40800000 0x0 0x00400000>;
riscv,ndev = <0x3>; riscv,ndev = <3>;
riscv,max-priority = <0x7>; //riscv,max-priority = <0x7>;
phandle = <0x3>; phandle = <0x3>;
}; };
/* Core Local Interruptor: It directly connects to the timer and /* Core Local Interruptor: It directly connects to the timer and