From 6155c7e3f8d94e58294b7becf7110b03430f9d71 Mon Sep 17 00:00:00 2001
From: Rodrigo Arias Mallo <rodrigo.arias@bsc.es>
Date: Mon, 8 Jul 2024 08:48:56 +0200
Subject: [PATCH] Try to fill cache details

---
 JOURNAL.md  | 36 ++++++++++++++++++++++++++++++++++++
 ox-plic.dts | 20 ++++++++++++++++++++
 2 files changed, 56 insertions(+)

diff --git a/JOURNAL.md b/JOURNAL.md
index c52d45a..3860946 100644
--- a/JOURNAL.md
+++ b/JOURNAL.md
@@ -679,4 +679,40 @@ Disabling clang as it is failing to build:
     error: 1 dependencies of derivation '/nix/store/b13shgqj7128rdsdzzp4qicqbzl0wnfw-system-path.drv' failed to build
     error: 1 dependencies of derivation '/nix/store/6qghlihqcyg6155309ldj5xm9m0v835i-nixos-system-nixos-riscv-24.11pre-git.drv' failed to build
     error: 1 dependencies of derivation '/nix/store/l2x18cih29r1kn6vi8imwhkyk98yhw4i-nix-shell-riscv64-unknown-linux-gnu-env.drv' failed to build
+
 <!--}}}-->
+
+### QUESTION: Missing cache information may affect?
+
+Other CPUs report the cache details in the DT. For example this one
+https://github.com/torvalds/linux/blob/master/arch/riscv/boot/dts/sifive/fu540-c000.dtsi#L45
+
+	cpu1: cpu@1 {
+		compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
+		d-cache-block-size = <64>;
+		d-cache-sets = <64>;
+		d-cache-size = <32768>;
+		d-tlb-sets = <1>;
+		d-tlb-size = <32>;
+		device_type = "cpu";
+		i-cache-block-size = <64>;
+		i-cache-sets = <64>;
+		i-cache-size = <32768>;
+		i-tlb-sets = <1>;
+		i-tlb-size = <32>;
+		mmu-type = "riscv,sv39";
+		reg = <1>;
+		riscv,isa = "rv64imafdc";
+		riscv,isa-base = "rv64i";
+		riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+				       "zifencei", "zihpm";
+		tlb-split;
+		next-level-cache = <&l2cache>;
+		cpu1_intc: interrupt-controller {
+			#interrupt-cells = <1>;
+			compatible = "riscv,cpu-intc";
+			interrupt-controller;
+		};
+	};
+
+We may want to add it to our DT to be sure that it has no effect.
diff --git a/ox-plic.dts b/ox-plic.dts
index 018c2e8..f66ce9a 100644
--- a/ox-plic.dts
+++ b/ox-plic.dts
@@ -27,6 +27,26 @@
 			riscv,isa = "rv64imafd";
 			mmu-type = "riscv,sv39";
 			tlb-split;
+
+			// OpenPiton+Ariane Platform
+			// L1I Size / Assoc:   16 kB / 4
+			// L1D Size / Assoc:   32 kB / 4
+			// L15 Size / Assoc:  128 kB / 8
+			// L2  Size / Assoc:  256 kB / 4
+			// L15/L1D Cacheline size 64
+
+			i-cache-block-size = <64>; // Guess
+			i-cache-sets = <4>;
+			i-cache-size = <16384>;
+			i-tlb-sets = <1>; // Guess
+			i-tlb-size = <32>; // Guess
+
+			d-cache-block-size = <64>; // Guess
+			d-cache-sets = <4>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>; // Guess
+			d-tlb-size = <32>; // Guess
+
 			phandle = <0x00000004>;
 			/* Hart-Level Interrupt Controller: Every interrupt is
 			 * ultimately routed through a hart's HLIC before it