diff --git a/overlay.nix b/overlay.nix
index bfbdbef..49c8f83 100644
--- a/overlay.nix
+++ b/overlay.nix
@@ -87,6 +87,7 @@ final: prev:
       #./sa-fpga-crt.patch
       #./sa-fpga-text-address.patch
       ./sa-fpga-uart.patch
+      ./sa-fpga-plic-registers.patch
     ];
     buildPhase = ''
       cd fpga_core_bridge/simulator/tests/c_tests/
diff --git a/sa-fpga-plic-registers.patch b/sa-fpga-plic-registers.patch
new file mode 100644
index 0000000..2ae8488
--- /dev/null
+++ b/sa-fpga-plic-registers.patch
@@ -0,0 +1,92 @@
+diff --git a/fpga_core_bridge/simulator/tests/c_tests/plic_supervisor/plic_supervisor_test.c b/fpga_core_bridge/simulator/tests/c_tests/plic_supervisor/plic_supervisor_test.c
+index 0cfa681..78d97cb 100644
+--- a/fpga_core_bridge/simulator/tests/c_tests/plic_supervisor/plic_supervisor_test.c
++++ b/fpga_core_bridge/simulator/tests/c_tests/plic_supervisor/plic_supervisor_test.c
+@@ -68,6 +68,48 @@ uintptr_t handle_trap(uint64_t cause, uint64_t epc, uintptr_t regs[32])
+   return epc;
+ }
+ 
++static void dumpregs(int machine)
++{
++	printf("Registers:");
++	if (machine) {
++		uint64_t mie;
++		asm volatile("csrr %0, mie" : "=r"(mie));
++		printf("\n    MIE: ");
++		printhex(mie);
++
++		uint64_t mip;
++		asm volatile("csrr %0, mip" : "=r"(mip));
++		printf("\n    MIP: ");
++		printhex(mip);
++
++		uint64_t mstatus;
++		asm volatile("csrr %0, mstatus" : "=r"(mstatus));
++		printf("\nMSTATUS: ");
++		printhex(mstatus);
++
++		uint64_t mideleg;
++		asm volatile("csrr %0, mideleg" : "=r"(mideleg));
++		printf("\nMIDELEG: ");
++		printhex(mideleg);
++	}
++
++	uint64_t sie;
++	asm volatile("csrr %0, sie" : "=r"(sie));
++	printf("\n    SIE: ");
++	printhex(sie);
++
++	uint64_t sip;
++	asm volatile("csrr %0, sip" : "=r"(sip));
++	printf("\n    SIP: ");
++	printhex(sip);
++
++	uint64_t sstatus;
++	asm volatile("csrr %0, sstatus" : "=r"(sstatus));
++	printf("\nSSTATUS: ");
++	printhex(sstatus);
++	printf("\n");
++}
++
+ // Define the bit positions for the external interrupt enable in mie and mideleg registers
+ #define SIE_SEIE (1 << 9)      // Supervisor External Interrupt Enable
+ #define MIDELEG_MEIE (1 << 11) // Delegate Machine External Interrupt to Supervisor
+@@ -156,16 +198,19 @@ void __attribute__((optimize("O0"))) switch_to_supervisor_mode(uint64_t* target_
+     asm volatile("mret");
+ }
+ 
+-uint64_t supervisor_mode_code() {
+-    int count = 0;
+-    while (1) {
+-        if (count == 10000) {
+-            uart_write_string("\nWaiting for interrupt in supervisor mode...");
+-            count = 0;
+-        }
+-        count++;
+-    }
+-    return 0;
++uint64_t supervisor_mode_code()
++{
++	uart_write_string("\nHello from supervisor mode...");
++	dumpregs(0);
++	int count = 0;
++	while (1) {
++		if (count == 10000) {
++			uart_write_string("\nWaiting for interrupt in supervisor mode...");
++			count = 0;
++		}
++		count++;
++	}
++	return 0;
+ }
+ 
+ void main(void) {
+@@ -181,6 +226,8 @@ void main(void) {
+     // Enable external timer interrupts
+     // enable_external_timer_interrupt();
+ 
++    dumpregs(1);
++
+     // Switch to supervisor mode and execute supervisor_mode_code
+     switch_to_supervisor_mode(&supervisor_mode_code);
+