From 4333f8074e6db4113ae2bf22e4273b1893c4f913 Mon Sep 17 00:00:00 2001
From: Rodrigo Arias Mallo <rodrigo.arias@bsc.es>
Date: Fri, 11 Oct 2024 11:01:48 +0200
Subject: [PATCH] Configure SPI addresses in header

We use the ENABLE_SPI toggle to also set the PLIC number of inputs.
---
 dts/lagarto_ox.dts | 18 +++++++++---------
 dts/lagarto_ox.h   | 35 ++++++++++++++++++++++++-----------
 2 files changed, 33 insertions(+), 20 deletions(-)

diff --git a/dts/lagarto_ox.dts b/dts/lagarto_ox.dts
index d3881b3..d9c41ce 100644
--- a/dts/lagarto_ox.dts
+++ b/dts/lagarto_ox.dts
@@ -205,7 +205,7 @@
 		 * property is described in
 		 * Documentation/devicetree/bindings/riscv/cpus.yaml
 		 */
-		clint: clint@40100000 {
+		clint: clint@CLINT_ADDR {
 			reg = /bits/ 64 <CLINT_ADDR CLINT_SIZE>;
 			reg-names = "control";
 			interrupts-extended = <&HLIC0 3>, <&HLIC0 7>;
@@ -217,8 +217,8 @@
 		/* There is another auxiliar clint (timer) at 40010000 for
 		 * tests, but we don't tell the kernel so we can use it for
 		 * testing interrupts manually. */
-		aux_timer: clint@40010000 {
-			reg = /bits/ 64 <0x0 0x40010000 0x0 0x00010000>;
+		aux_timer: clint@AUXTIMER_ADDR {
+			reg = /bits/ 64 <AUXTIMER_ADDR AUXTIMER_SIZE>;
 			reg-names = "control";
 			interrupts = <4>; /* PLIC input source 4 */
 			interrupt-parent = <&PLIC>;
@@ -227,23 +227,23 @@
 #endif
 
 #ifdef ENABLE_SPI
-		uart16750: serial@40005000 {
+		serial@UART2_ADDR {
 			compatible = "ns16750";
-			reg = <0x00000000 0x40005000 0x00000000 0x00001000>;
+			reg = /bits/ 64 <UART2_ADDR UART2_SIZE>;
 			interrupt-parent = <&PLIC>;
 			interrupts = <5>;
 			clock-frequency = <CPU_FREQ>;
-			current-speed = <0x0001c200>;
+			current-speed = <UART2_SPEED>;
 			status = "okay";
 		};
-		spi0: spi@40007000 {
+		spi@SPI_ADDR {
 			compatible = "ti,keystone-spi";
-			reg = <0x00000000 0x40007000 0x00000000 0x00001000>;
+			reg = /bits/ 64 <SPI_ADDR SPI_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			interrupt-parent = <&PLIC>;
 			interrupt-names = "intvec0", "intvec1";
-			interrupts = <6 0>, <0x00000007 0>;
+			interrupts = <6 0>, <7 0>;
 			ti,davinci-spi-intr-line = <0>;
 			spi-max-frequency = <24000000>;
 			loopback-mode = <1>;
diff --git a/dts/lagarto_ox.h b/dts/lagarto_ox.h
index 92de7d4..4892738 100644
--- a/dts/lagarto_ox.h
+++ b/dts/lagarto_ox.h
@@ -1,3 +1,13 @@
+/* Toggles */
+
+#define ENABLE_UART0
+#define ENABLE_UART1
+#define ENABLE_ETHERNET
+#define ENABLE_AXIDMA
+#define ENABLE_PLIC
+#define ENABLE_CLINT
+//#define ENABLE_SPI
+
 #define CPU_FREQ	50000000 /* 50 MHz */
 /* FIXME: The real RTC frequency is around half that, as the divider was wrongly
  * configured. So for now lets use the real frequency:
@@ -22,6 +32,14 @@
 #define UART1_ADDR	0x40003000
 #define UART1_SIZE	0x00001000
 
+/* UART2 via SPI */
+#define UART2_SPEED	UART0_SPEED
+#define UART2_ADDR	0x40005000
+#define UART2_SIZE	0x00001000
+
+#define SPI_ADDR	0x40007000
+#define SPI_SIZE	0x00001000
+
 #define AUXTIMER_ADDR	0x40010000
 #define AUXTIMER_SIZE	0x00010000
 
@@ -36,7 +54,12 @@
 
 #define PLIC_ADDR	0x40800000
 #define PLIC_SIZE	0x00400000
-#define PLIC_NDEV	4
+
+#ifdef ENABLE_SPI
+# define PLIC_NDEV	7 /* extra UART2 + 2 x SPI */
+#else
+# define PLIC_NDEV	4
+#endif
 
 #define ETHPOOL_ADDR	0x60000000
 #define ETHPOOL_SIZE	0x10000000
@@ -51,13 +74,3 @@
 
 #define PMEM_ADDR	0x1c0000000
 #define PMEM_SIZE	0x0c0000000
-
-/* Toggles */
-
-#define ENABLE_UART0
-#define ENABLE_UART1
-#define ENABLE_ETHERNET
-#define ENABLE_AXIDMA
-#define ENABLE_PLIC
-#define ENABLE_CLINT
-//#define ENABLE_SPI