rarias/nixos-riscv
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Move the pmem closer to the RAM memory

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Continues stuck in switch_root.
This commit is contained in:
Rodrigo Arias 2024-07-01 14:53:37 +02:00
parent 917cbf3439
commit 046f017b70
2 changed files with 10 additions and 9 deletions
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2
fpga/env.sh
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@ -41,7 +41,7 @@ function setup_meep()
export FPGACTL_BOOTLOADER_ADDR=$((0x80000000+$delta_addr)) export FPGACTL_BOOTLOADER_ADDR=$((0x80000000+$delta_addr))
export FPGACTL_KERNEL_ADDR=$((0x84000000+$delta_addr)) export FPGACTL_KERNEL_ADDR=$((0x84000000+$delta_addr))
export FPGACTL_INITRD_ADDR=$((0x8c300000+$delta_addr)) export FPGACTL_INITRD_ADDR=$((0x8c300000+$delta_addr))
export FPGACTL_ROOTFS_ADDR=$((0x1bff00000+$delta_addr)) export FPGACTL_ROOTFS_ADDR=$((0x100000000+$delta_addr))
} }
hostname=$(hostname) hostname=$(hostname)

17
ox-plic.dts
View File

@ -4,9 +4,9 @@
#size-cells = <2>; /* 64 bits memory addresses */ #size-cells = <2>; /* 64 bits memory addresses */
compatible = "riscv,rv64i"; compatible = "riscv,rv64i";
model = "Barcelona Supercomputing Center - Lagarto Ox (NixOS)"; model = "Barcelona Supercomputing Center - Lagarto Ox (NixOS)";
chosen { // chosen {
bootargs = "earlyprintk ignore_loglevel earlycon=sbi console=hvc0 root=/dev/pmem0p1 ro init=/bin/bash"; // bootargs = "earlyprintk ignore_loglevel earlycon=sbi console=hvc0 root=/dev/pmem0p1 ro init=/bin/bash";
}; // };
cpus { cpus {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
@ -44,9 +44,10 @@
* *
* [0x0_6000_0000, 0x0_7000_0000) -> DMA pool (256 MiB) * [0x0_6000_0000, 0x0_7000_0000) -> DMA pool (256 MiB)
* [0x0_7000_0000, 0x0_8000_0000) -> DMA pool (256 MiB) * [0x0_7000_0000, 0x0_8000_0000) -> DMA pool (256 MiB)
* [0x0_8000_0000, 0x0_7ff0_0000) -> RAM memory (~2 GiB) * [0x0_8000_0000, 0x0_fff0_0000) -> RAM memory (2047 MiB)
* [0x0_7ff0_0000, 0x1_bff0_0000) -> Empty * [0x0_fff0_0000, 0x1_0000_0000) -> Empty (1 MiB)
* [0x1_bff0_0000, 0x2_8000_0000) -> PMEM (3 GiB) * [0x1_0000_0000, 0x1_c000_0000) -> PMEM (3072 MiB)
* [0x1_c000_0000, 0x2_8000_0000) -> Empty (3072 MiB)
*/ */
memory@80000000 { memory@80000000 {
device_type = "memory"; device_type = "memory";
@ -71,14 +72,14 @@
// clock-frequency = <0x09502f90>; // clock-frequency = <0x09502f90>;
// phandle = <0x00000002>; // phandle = <0x00000002>;
// }; // };
pmem@1bff00000 { pmem@100000000 {
/* volatile; This property indicates that this region is /* volatile; This property indicates that this region is
* actually backed by non-persistent memory. This lets the OS * actually backed by non-persistent memory. This lets the OS
* know that it may skip the cache flushes required to ensure * know that it may skip the cache flushes required to ensure
* data is made persistent after a write. */ * data is made persistent after a write. */
volatile; volatile;
compatible = "pmem-region"; compatible = "pmem-region";
reg = <0x1 0xbff00000 0x0 0xc0100000>; reg = <0x1 0x00000000 0x0 0xc0000000>;
}; };
soc { soc {
#address-cells = <0x00000002>; #address-cells = <0x00000002>;