Add plic claim baremetal test

overlay.nix

@@ -45,8 +45,8 @@ final: prev:
     name = "sa-fpga-tests";
     src = builtins.fetchGit {
       url = "git@gitlab-internal.bsc.es:hwdesign/rtl/core-tile/sa-fpga.git";
-      rev = "afe0372413a94fff279ca5d5002c3e999ac8defb";
-      ref = "ft/sv_eirq";
+      rev = "720be4f1f5dd0ef963135992578be2ab55fb5537";
+      ref = "main";
     };
     dontConfigure = true;
     patches = [
@@ -54,6 +54,7 @@ final: prev:
       #./patches/sa-fpga-text-address.patch
       ./patches/sa-fpga-uart.patch
       ./patches/sa-fpga-plic-registers.patch
+      ./patches/sa-fpga-add-plic-claim-test.patch
     ];
     buildPhase = ''
       cd fpga_core_bridge/simulator/tests/c_tests/