forked from rarias/nixos-riscv
Increase RAM and improve DT
This commit is contained in:
@@ -10,6 +10,7 @@ clean:
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%.pp.dts: %.dts *.h
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$(CC) $(CPPFLAGS) $< -o $@
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sed -i 's/@0x0*/@/' $@
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%.dtb: %.pp.dts
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dtc -O dtb -o $@ $^
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@@ -7,21 +7,13 @@
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compatible = "riscv,rv64i";
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model = "Barcelona Supercomputing Center - Lagarto Ox (NixOS)";
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aliases {
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serial0 = &uart_console; // ttyS0
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// serial1 = &uart_testing; // ttyS1
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};
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// chosen {
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// bootargs = "earlyprintk ignore_loglevel earlycon=sbi console=hvc0 root=/dev/pmem0p1 ro init=/bin/bash";
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// };
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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timebase-frequency = <RTC_CLOCK_FREQUENCY>;
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timebase-frequency = <RTC_FREQ>;
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CPU0: cpu@0 {
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clock-frequency = <CPU_CLOCK_FREQUENCY>;
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clock-frequency = <CPU_FREQ>;
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device_type = "cpu";
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reg = <0>;
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status = "okay";
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@@ -30,13 +22,6 @@
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mmu-type = "riscv,sv39";
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tlb-split;
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// OpenPiton+Ariane Platform
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// L1I Size / Assoc: 16 kB / 4
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// L1D Size / Assoc: 32 kB / 4
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// L15 Size / Assoc: 128 kB / 8
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// L2 Size / Assoc: 256 kB / 4
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// L15/L1D Cacheline size 64
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i-cache-block-size = <64>; // Guess
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i-cache-sets = <4>;
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i-cache-size = <16384>;
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@@ -49,7 +34,6 @@
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d-tlb-sets = <1>; // Guess
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d-tlb-size = <32>; // Guess
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phandle = <0x00000004>;
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/* Hart-Level Interrupt Controller: Every interrupt is
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* ultimately routed through a hart's HLIC before it
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* interrupts that hart. */
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@@ -57,7 +41,6 @@
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#interrupt-cells = <1>;
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interrupt-controller; /* Receives interrupts */
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compatible = "riscv,cpu-intc";
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phandle = <0x5>;
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};
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};
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cpu-map {
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@@ -68,109 +51,111 @@
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};
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};
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};
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/* Memory layout:
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*
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* [0x0_6000_0000, 0x0_7000_0000) -> DMA pool (256 MiB)
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* [0x0_7000_0000, 0x0_8000_0000) -> DMA pool (256 MiB)
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* [0x0_8000_0000, 0x0_b000_0000) -> RAM memory (768 MiB)
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* [0x0_b000_0000, 0x0_c000_0000) -> Broken? (256 MiB)
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* [0x0_c000_0000, 0x1_0000_0000) -> Empty (1024 MiB)
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* [0x1_0000_0000, 0x1_c000_0000) -> PMEM (3072 MiB)
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* [0x1_c000_0000, 0x2_8000_0000) -> Empty (3072 MiB)
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*/
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memory@80000000 {
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memory@MEM_ADDR {
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device_type = "memory";
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reg = <0x0 0x80000000 0x0 0x30000000>;
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reg = /bits/ 64 <MEM_ADDR MEM_SIZE>;
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};
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reserved-memory {
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#address-cells = <2>; /* Starting address and size */
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#size-cells = <2>; /* 64 bits memory addresses */
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ranges;
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eth_pool: dma_pool@60000000 {
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reg = <0x0 0x60000000 0x0 0x10000000>;
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eth_pool: dma_pool@ETHPOOL_ADDR {
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reg = /bits/ 64 <ETHPOOL_ADDR ETHPOOL_SIZE>;
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compatible = "shared-dma-pool";
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};
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onic_pool: dma_pool@70000000 {
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reg = <0x0 0x70000000 0x0 0x10000000>;
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onic_pool: dma_pool@ONICPOOL_ADDR {
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reg = /bits/ 64 <ONICPOOL_ADDR ONICPOOL_SIZE>;
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compatible = "shared-dma-pool";
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};
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};
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dma_clk: dma_clk {
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compatible = "fixed-clock";
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#clock-cells = <0x00000000>;
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clock-frequency = <0x09502f90>;
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phandle = <0x00000002>;
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};
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pmem@100000000 {
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pmem@PMEM_ADDR {
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/* volatile; This property indicates that this region is
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* actually backed by non-persistent memory. This lets the OS
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* know that it may skip the cache flushes required to ensure
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* data is made persistent after a write. */
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volatile;
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compatible = "pmem-region";
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reg = <0x1 0x00000000 0x0 0xc0000000>;
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reg = /bits/ 64 <PMEM_ADDR PMEM_SIZE>;
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};
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soc {
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#address-cells = <0x00000002>;
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#size-cells = <0x00000002>;
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "BSC,Lagarto-ox-soc", "simple-bus";
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ranges;
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/* For bitstream e97dd7b2-397f-11ef-abe0-bbd201a5a630 with two
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* consoles */
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#ifdef ENABLE_UART0
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/* The serial for the kernel console */
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uart_console: serial@UART0_ADDR_HEX {
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uart_console: serial@UART0_ADDR {
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compatible = "ns16550";
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reg = <0x0 UART0_ADDR 0x0 0x1000>;
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reg = /bits/ 64 <UART0_ADDR UART0_SIZE>;
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reg-shift = <2>;
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/* No interrupts for this UART, use console=hvc0 */
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/* This clock is the SERIAL_CLK */
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clock-frequency = <CPU_CLOCK_FREQUENCY>;
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current-speed = <UART_SPEED>;
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clock-frequency = <CPU_FREQ>;
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current-speed = <UART0_SPEED>;
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status = "okay";
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};
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#endif /* ENABLE_UART0 */
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#ifdef ENABLE_UART1
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/* The serial for interrupt tests */
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uart_testing: serial@40003000 {
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uart_testing: serial@UART1_ADDR {
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compatible = "ns16550";
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reg = <0x0 0x40003000 0x0 0x1000>;
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reg = /bits/ 64 <UART1_ADDR UART1_SIZE>;
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reg-shift = <2>;
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/* Output interrupt 1 (the first one) */
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interrupts = <1>;
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interrupt-parent = <&PLIC>;
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clock-frequency = <CPU_CLOCK_FREQUENCY>;
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current-speed = <UART_SPEED>;
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clock-frequency = <CPU_FREQ>;
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current-speed = <UART1_SPEED>;
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status = "okay";
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};
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#endif /* ENABLE_UART1 */
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#ifdef ENABLE_ETHERNET
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ethernet0 {
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xlnx,rxmem = <0x000005f2>;
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carv,mtu = <0x000005dc>;
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carv,no-mac;
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device_type = "network";
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// 02:$node:00:01:00:$fpga -> 02:05:00:01:00:02
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// 10.5.1.$N/16 -> 10.5.1.184/16
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// N = 150 + ($node - 1) * 8 + $fpga
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local-mac-address = [00 00 00 00 00 00];
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axistream-connected = <&axi_dma>;
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compatible = "xlnx,xxv-ethernet-1.0-carv";
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memory-region = <ð_pool>;
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xlnx,rxmem = <1522>;
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carv,mtu = <1500>;
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carv,no-mac;
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device_type = "network";
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// 02:$node:00:01:00:$fpga -> 02:05:00:01:00:02
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// 10.5.1.$N/16 -> 10.5.1.184/16
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// N = 150 + ($node - 1) * 8 + $fpga
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local-mac-address = [00 00 00 00 00 00];
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axistream-connected = <&axi_dma>;
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compatible = "xlnx,xxv-ethernet-1.0-carv";
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memory-region = <ð_pool>;
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};
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#endif /* ENABLE_ETHERNET */
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axi_dma: dma@40400000 {
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#ifdef ENABLE_AXIDMA
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dma_clk: dma_clk {
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compatible = "fixed-clock";
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#clock-cells = <0x0>;
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clock-frequency = <AXIDMA_FREQ>;
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};
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axi_dma: dma@AXIDMA_ADDR {
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reg = /bits/ 64 <AXIDMA_ADDR AXIDMA_SIZE>;
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reg-shift = <2>;
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#address-cells = <2>;
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#size-cells = <2>;
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xlnx,include-dre;
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#dma-cells = <0x00000001>;
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#dma-cells = <0x1>;
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compatible = "xlnx,axi-dma-1.00.a";
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clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", "m_axi_sg_aclk";
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clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk",
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"m_axi_s2mm_aclk", "m_axi_sg_aclk";
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clocks = <&dma_clk>, <&dma_clk>, <&dma_clk>, <&dma_clk>;
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reg = <0x00000000 0x40400000 0x00000000 0x00400000>;
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interrupt-names = "mm2s_introut", "s2mm_introut";
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interrupt-parent = <&PLIC>;
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interrupts = <2 3>;
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xlnx,addrwidth = <0x28>;
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xlnx,include-sg;
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xlnx,sg-length-width = <0x17>;
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dma-channel@40400000 {
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dma-channel@AXIDMA_CH0 {
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reg = /bits/ 64 <AXIDMA_CH0 0x30>;
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compatible = "xlnx,axi-dma-mm2s-channel";
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dma-channels = <0>;
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interrupts = <2>;
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@@ -178,7 +163,8 @@
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xlnx,device-id = <0x0>;
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xlnx,include-dre;
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};
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dma-channel@40400030 {
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dma-channel@AXIDMA_CH1 {
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reg = /bits/ 64 <AXIDMA_CH1 0x30>;
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compatible = "xlnx,axi-dma-s2mm-channel";
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dma-channels = <1>;
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interrupts = <3>;
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@@ -187,10 +173,13 @@
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xlnx,include-dre;
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};
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};
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#endif /* ENABLE_AXIDMA */
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#ifdef ENABLE_PLIC
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/* Platform-Level Interrupt Controller: Delivers interrupts to
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* HARTs. */
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PLIC: plic@40800000 {
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PLIC: plic@PLIC_ADDR {
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reg = /bits/ 64 <PLIC_ADDR PLIC_SIZE>;
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compatible = "riscv,plic0";
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interrupt-controller; /* Receives interrupts */
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#address-cells = <0>;
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@@ -201,11 +190,12 @@
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* - context 1: supervisor mode external interrupt (9)
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*/
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interrupts-extended = <&HLIC0 11>, <&HLIC0 9>;
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reg = < 0x0 0x40800000 0x0 0x00400000>;
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riscv,ndev = <4>;
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riscv,ndev = <PLIC_NDEV>;
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//riscv,max-priority = <0x7>;
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phandle = <0x3>;
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};
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#endif /* ENABLE_PLIC */
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#ifdef ENABLE_CLINT
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/* Core Local Interruptor: It directly connects to the timer and
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* inter-processor interrupt lines of various HARTs (or CPUs) so
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* RISC-V per-HART (or per-CPU) local interrupt controller is
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@@ -216,32 +206,33 @@
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* Documentation/devicetree/bindings/riscv/cpus.yaml
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*/
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clint: clint@40100000 {
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reg = <0x0 0x40100000 0x0 0x00010000>;
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reg = /bits/ 64 <CLINT_ADDR CLINT_SIZE>;
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reg-names = "control";
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interrupts-extended = <&HLIC0 3>, <&HLIC0 7>;
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compatible = "riscv,clint0";
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};
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#endif /* ENABLE_CLINT */
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#if 0
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/* There is another auxiliar clint (timer) at 40010000 for
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* tests, but we don't tell the kernel so we can use it for
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* testing interrupts manually. */
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#if 0
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aux_timer: clint@40010000 {
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reg = <0x0 0x40010000 0x0 0x00010000>;
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reg = /bits/ 64 <0x0 0x40010000 0x0 0x00010000>;
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reg-names = "control";
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interrupts = <4>; /* PLIC input source 4 */
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interrupt-parent = <&PLIC>;
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compatible = "riscv,clint0";
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};
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#endif
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#endif
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#ifdef ENABLE_SPI
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#ifdef ENABLE_SPI
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uart16750: serial@40005000 {
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compatible = "ns16750";
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reg = <0x00000000 0x40005000 0x00000000 0x00001000>;
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interrupt-parent = <&PLIC>;
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interrupts = <5>;
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clock-frequency = <CPU_CLOCK_FREQUENCY>;
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clock-frequency = <CPU_FREQ>;
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current-speed = <0x0001c200>;
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status = "okay";
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};
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@@ -258,6 +249,7 @@
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loopback-mode = <1>;
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status = "okay";
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};
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#endif
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#endif /* ENABLE_SPI */
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};
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};
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@@ -1,21 +1,62 @@
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/* CPU is at 50 MHz */
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#define CPU_CLOCK_FREQUENCY 50000000
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/* The RTC timer is clocked at the CPU frequency / 1525, so
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* around 32786.88 Hz */
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//#define RTC_CLOCK_FREQUENCY 32786
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#define CPU_FREQ 50000000 /* 50 MHz */
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/* FIXME: The real RTC frequency is around half that, as the divider was wrongly
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* configured. So for now lets use the real frequency:
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* 50e6 / (1525*2) = 16393.44262295082 -> 16393 Hz */
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#define RTC_CLOCK_FREQUENCY 16393
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#define RTC_FREQ 16393
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#define UART_SPEED 115200
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#define UART0_ADDR 0x40001000
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#define UART0_ADDR_HEX 40001000
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/* Memory layout:
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*
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* [0x0_4000_0000, 0x0_6000_0000) -> IO (512 MiB)
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* [0x0_6000_0000, 0x0_7000_0000) -> DMA pool (256 MiB)
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* [0x0_7000_0000, 0x0_8000_0000) -> DMA pool (256 MiB)
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* [0x0_8000_0000, 0x1_c000_0000) -> RAM memory (5 GiB)
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* [0x1_c000_0000, 0x2_8000_0000) -> PMEM (3 GiB)
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*/
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#define PLIC_ADDR 0x40800000
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#define UART_ADDR 0x40001000
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#define UART0_SPEED 115200
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#define UART0_ADDR 0x40001000
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#define UART0_SIZE 0x00001000
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#define UART1_SPEED UART0_SPEED
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#define UART1_ADDR 0x40003000
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#define UART1_SIZE 0x00001000
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#define AUXTIMER_ADDR 0x40010000
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#define AUXTIMER_SIZE 0x00010000
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#define CLINT_ADDR 0x40100000
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#define CLINT_SIZE 0x00010000
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#define AXIDMA_ADDR 0x40400000
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#define AXIDMA_SIZE 0x00400000
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#define AXIDMA_CH0 0x40400000
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#define AXIDMA_CH1 0x40400030
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#define AXIDMA_FREQ 156250000
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#define PLIC_ADDR 0x40800000
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#define PLIC_SIZE 0x00400000
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#define PLIC_NDEV 4
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#define ETHPOOL_ADDR 0x60000000
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#define ETHPOOL_SIZE 0x10000000
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#define ONICPOOL_ADDR 0x70000000
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#define ONICPOOL_SIZE 0x10000000
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/* Notice addresses > 32 bits from here */
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#define MEM_ADDR 0x080000000
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#define MEM_SIZE 0x140000000
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#define PMEM_ADDR 0x1c0000000
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#define PMEM_SIZE 0x0c0000000
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/* Toggles */
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#define ENABLE_UART0
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#define ENABLE_UART1
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#define ENABLE_ETHERNET
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#define ENABLE_AXIDMA
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#define ENABLE_PLIC
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#define ENABLE_CLINT
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//#define ENABLE_SPI
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