diff --git a/ox-plic.dts b/ox-plic.dts index 2735352..2423b87 100644 --- a/ox-plic.dts +++ b/ox-plic.dts @@ -1,31 +1,42 @@ /dts-v1/; / { - #address-cells = <0x00000002>; - #size-cells = <0x00000002>; + #address-cells = <2>; + #size-cells = <2>; /* 64 bits memory addresses */ compatible = "riscv,rv64i"; model = "Barcelona Supercomputing Center - Lagarto Ox (NixOS)"; chosen { bootargs = "earlyprintk ignore_loglevel earlycon=sbi console=hvc0 root=/dev/pmem0p1 ro init=/bin/bash"; }; cpus { - #address-cells = <0x00000001>; - #size-cells = <0x00000000>; - timebase-frequency = <0x0000c350>; + #address-cells = <1>; + #size-cells = <0>; + /* Timer */ + timebase-frequency = <50000>; /* 50 kHz */ CPU0: cpu@0 { - clock-frequency = <0x02FAF080>; + clock-frequency = <50000000>; /* 50 MHz */ device_type = "cpu"; - reg = <0x00000000>; + reg = <0>; status = "okay"; compatible = "riscv"; riscv,isa = "rv64imafd"; mmu-type = "riscv,sv39"; tlb-split; phandle = <0x00000004>; - L3: interrupt-controller { - #interrupt-cells = <0x00000001>; - interrupt-controller; + /* Hart-Level Interrupt Controller: Every interrupt is + * ultimately routed through a hart's HLIC before it + * interrupts that hart. */ + HLIC0: interrupt-controller { + #interrupt-cells = <1>; + interrupt-controller; /* Receives interrupts */ compatible = "riscv,cpu-intc"; - phandle = <0x00000005>; + phandle = <0x5>; + }; + }; + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; }; }; }; @@ -39,29 +50,27 @@ */ memory@80000000 { device_type = "memory"; - reg = <0x00000000 0x80000000 0x00000000 0x7ff00000>; + reg = <0x0 0x80000000 0x0 0x7ff00000>; }; reserved-memory { - #address-cells = <0x00000002>; - #size-cells = <0x00000002>; + #address-cells = <2>; /* Starting address and size */ + #size-cells = <2>; /* 64 bits memory addresses */ ranges; eth_pool: dma_pool@60000000 { - reg = <0x00000000 0x60000000 0x00000000 0x10000000>; + reg = <0x0 0x60000000 0x0 0x10000000>; compatible = "shared-dma-pool"; - phandle = <0x00000001>; }; onic_pool: dma_pool@70000000 { - reg = <0x00000000 0x70000000 0x00000000 0x10000000>; + reg = <0x0 0x70000000 0x0 0x10000000>; compatible = "shared-dma-pool"; - phandle = <0x00000006>; }; }; - eth0_clk: eth0_clk { - compatible = "fixed-clock"; - #clock-cells = <0x00000000>; - clock-frequency = <0x09502f90>; - phandle = <0x00000002>; - }; +// eth0_clk: eth0_clk { +// compatible = "fixed-clock"; +// #clock-cells = <0x00000000>; +// clock-frequency = <0x09502f90>; +// phandle = <0x00000002>; +// }; pmem@1bff00000 { /* volatile; This property indicates that this region is * actually backed by non-persistent memory. This lets the OS @@ -69,7 +78,7 @@ * data is made persistent after a write. */ volatile; compatible = "pmem-region"; - reg = <0x00000001 0xbff00000 0x00000000 0xc0100000>; + reg = <0x1 0xbff00000 0x0 0xc0100000>; }; soc { #address-cells = <0x00000002>; @@ -78,76 +87,87 @@ ranges; SERIAL: serial@40001000 { compatible = "ns16550"; - reg = <0x0 0x40001000 0x0 0x00000100>; - interrupts = <0>; - /*port-number = <0>;*/ + reg = <0x0 0x40001000 0x0 0x100>; + interrupts = <0>; /* Output interrupt 0 */ + interrupt-parent = <&PLIC>; reg-shift = <2>; clock-frequency = <50000000>; current-speed = <115200>; status = "okay"; - phandle = <0x00000007>; }; - ethernet0 { - xlnx,rxmem = <0x000005f2>; - carv,mtu = <0x000005dc>; - carv,no-mac; - device_type = "network"; - local-mac-address = [02 05 00 01 00 05]; - axistream-connected = <0x000000fe>; - compatible = "xlnx,xxv-ethernet-1.0-carv"; - memory-region = <ð_pool>; - }; - dma@40400000 { - xlnx,include-dre; - phandle = <0x000000fe>; - #dma-cells = <0x00000001>; - compatible = "xlnx,axi-dma-1.00.a"; - clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", "m_axi_sg_aclk"; - clocks = <ð0_clk>, <ð0_clk>, <ð0_clk>, <ð0_clk>; - reg = <0x00000000 0x40400000 0x00000000 0x00400000>; - interrupt-names = "mm2s_introut", "s2mm_introut"; - interrupt-parent = <&PLIC0>; - interrupts = <0x00000002 0x00000003>; - xlnx,addrwidth = <0x00000028>; - xlnx,include-sg; - xlnx,sg-length-width = <0x00000017>; - dma-channel@40400000 { - compatible = "xlnx,axi-dma-mm2s-channel"; - dma-channels = <0x00000000>; - interrupts = <0x00000002>; - xlnx,datawidth = <0x00000040>; - xlnx,device-id = <0x00000000>; - xlnx,include-dre; - }; - dma-channel@40400030 { - compatible = "xlnx,axi-dma-s2mm-channel"; - dma-channels = <0x00000001>; - interrupts = <0x00000003>; - xlnx,datawidth = <0x00000040>; - xlnx,device-id = <0x00000000>; - xlnx,include-dre; - }; - }; - clint@40002000 { - reg-names = "control"; - interrupts-extended = - <&CPU0 0x3>, <&CPU0 0x7>, - <&L3 0x3>, <&L3 0x7>, - <&onic_pool 0x3>, <&onic_pool 0x7>, - <&SERIAL 0x3>, <&SERIAL 0x7>; - compatible = "riscv,clint0"; - #interrupt-cells = <0x00000001>; - reg = <0x00000000 0x40002000 0x00000000 0x000c0000>; - }; - PLIC0: plic@40800000 { - #interrupt-cells = <1>; + +// ethernet0 { +// xlnx,rxmem = <0x000005f2>; +// carv,mtu = <0x000005dc>; +// carv,no-mac; +// device_type = "network"; +// local-mac-address = [02 05 00 01 00 05]; +// axistream-connected = <0x000000fe>; +// compatible = "xlnx,xxv-ethernet-1.0-carv"; +// memory-region = <ð_pool>; +// }; +// dma@40400000 { +// xlnx,include-dre; +// phandle = <0x000000fe>; +// #dma-cells = <0x00000001>; +// compatible = "xlnx,axi-dma-1.00.a"; +// clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", "m_axi_sg_aclk"; +// clocks = <ð0_clk>, <ð0_clk>, <ð0_clk>, <ð0_clk>; +// reg = <0x00000000 0x40400000 0x00000000 0x00400000>; +// interrupt-names = "mm2s_introut", "s2mm_introut"; +// interrupt-parent = <&PLIC>; +// interrupts = <2 3>; +// xlnx,addrwidth = <0x00000028>; +// xlnx,include-sg; +// xlnx,sg-length-width = <0x00000017>; +// dma-channel@40400000 { +// compatible = "xlnx,axi-dma-mm2s-channel"; +// dma-channels = <0x00000000>; +// interrupts = <0x00000002>; +// xlnx,datawidth = <0x00000040>; +// xlnx,device-id = <0x00000000>; +// xlnx,include-dre; +// }; +// dma-channel@40400030 { +// compatible = "xlnx,axi-dma-s2mm-channel"; +// dma-channels = <0x00000001>; +// interrupts = <0x00000003>; +// xlnx,datawidth = <0x00000040>; +// xlnx,device-id = <0x00000000>; +// xlnx,include-dre; +// }; +// }; + + /* Platform-Level Interrupt Controller: Delivers interrupts to + * HARTs. */ + PLIC: plic@40800000 { compatible = "riscv,plic0"; - interrupt-controller; - interrupts-extended = <&L3 3 &L3 7>; - reg = < 0x00000000 0x40800000 0x00000000 0x00400000>; - riscv,ndev = <0x00000003>; - riscv,max-priority = <0x00000007>; - phandle = <0x00000003>; + interrupt-controller; /* Receives interrupts */ + #interrupt-cells = <1>; + /* Sends interrupts to HART interrupt controllers */ + interrupts-extended = <&HLIC0 3 &HLIC0 7>; + reg = < 0x0 0x40800000 0x0 0x00400000>; + riscv,ndev = <0x3>; + riscv,max-priority = <0x7>; + phandle = <0x3>; + }; + /* Core Local Interruptor: It directly connects to the timer and + * inter-processor interrupt lines of various HARTs (or CPUs) so + * RISC-V per-HART (or per-CPU) local interrupt controller is + * the parent interrupt controller for CLINT device. The clock + * frequency of CLINT is specified via "timebase-frequency" DT + * property of "/cpus" DT node. The "timebase-frequency" DT + * property is described in + * Documentation/devicetree/bindings/riscv/cpus.yaml + */ + timer@40002000 { + reg = <0x0 0x40002000 0x0 0x000c0000>; + reg-names = "control"; + interrupts-extended = <&HLIC0 3>, <&HLIC0 7>; + /*<&CPU0 0x3>, <&CPU0 0x7>,*/ + /*<&onic_pool 0x3>, <&onic_pool 0x7>,*/ + /*<&SERIAL 0x3>, <&SERIAL 0x7>*/ + compatible = "riscv,clint0"; }; }; };